Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

synth: Make synthesize_rtl emit a VerilogInfo provider #362

Merged
merged 2 commits into from
Nov 7, 2024
Merged

synth: Make synthesize_rtl emit a VerilogInfo provider #362

merged 2 commits into from
Nov 7, 2024

Commits on Nov 1, 2024

  1. synth: Make synthesize_rtl emit a VerilogInfo provider 

    Lets you do gate level sims easier if this rule can be passed
as if it were a verilog_library

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
    @QuantamHD
    QuantamHD committed Nov 1, 2024
    Configuration menu
    Copy the full SHA
    2b372e7 View commit details
    Browse the repository at this point in the history

Commits on Nov 2, 2024

  1. reformat bzl 

    Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
    @QuantamHD
    QuantamHD committed Nov 2, 2024
    Configuration menu
    Copy the full SHA
    8548293 View commit details
    Browse the repository at this point in the history