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Merge pull request #370 from spurserh/main
Lint #1135: Commit 9975e10 pushed by QuantamHD
November 29, 2024 18:28 15s main
November 29, 2024 18:28 15s
Add extra_tcl_command argument to synthesize_rtl rule.
Lint #1134: Pull request #370 synchronize by spurserh
November 29, 2024 18:00 20s spurserh:main
November 29, 2024 18:00 20s
Add extra_tcl_command argument to synthesize_rtl rule.
Lint #1133: Pull request #370 opened by spurserh
November 27, 2024 20:47 12s spurserh:main
November 27, 2024 20:47 12s
Merge pull request #369 from hdl/benchmark
Lint #1132: Commit 5eeb393 pushed by QuantamHD
November 21, 2024 07:10 15s main
November 21, 2024 07:10 15s
Report fmax and actual clock period if SDC differs from bazel parameter
Lint #1131: Pull request #369 opened by mikesinouye
November 20, 2024 23:12 17s benchmark
November 20, 2024 23:12 17s
Use a more straightforward scientific notation.
Lint #1130: Commit 2c8a03d pushed by mikesinouye
November 20, 2024 23:10 12s benchmark
November 20, 2024 23:10 12s
Use unique proto ID.
Lint #1129: Commit fec9bf8 pushed by mikesinouye
November 20, 2024 23:09 14s benchmark
November 20, 2024 23:09 14s
November 20, 2024 23:07 12s
Merge pull request #368 from hdl/drt
Lint #1127: Commit ad802c7 pushed by QuantamHD
November 19, 2024 22:11 11s main
November 19, 2024 22:11 11s
Support newer builds of OpenROAD which expect a string parameter in r…
Lint #1126: Pull request #368 opened by mikesinouye
November 19, 2024 21:36 17s drt
drt
November 19, 2024 21:36 17s
drt
November 19, 2024 21:35 12s
verilog: adds support for include headers
Lint #1124: Pull request #367 opened by filmil
November 11, 2024 07:51 Action required filmil:add-includedir
November 11, 2024 07:51 Action required
Use fewer threads when running openroad.
Lint #1123: Pull request #366 opened by grebe
November 7, 2024 22:16 12s grebe:num_threads
November 7, 2024 22:16 12s
synth: Make synthesize_rtl emit a VerilogInfo provider (#362)
Lint #1122: Commit ca650bf pushed by mikesinouye
November 7, 2024 17:05 13s main
November 7, 2024 17:05 13s
Add rules for DSim
Lint #1121: Pull request #365 opened by mkurc-ant
November 6, 2024 13:04 14s antmicro:DSim-rules
November 6, 2024 13:04 14s
Merge pull request #364 from grebe/local_cts
Lint #1120: Commit 7d85930 pushed by QuantamHD
November 5, 2024 23:15 16s main
November 5, 2024 23:15 16s
Add option to run clock tree synthesis locally.
Lint #1119: Pull request #364 opened by grebe
November 5, 2024 22:30 17s grebe:local_cts
November 5, 2024 22:30 17s
Fix cell utilization report for place and route. (#363)
Lint #1118: Commit a6b6eff pushed by mikesinouye
November 4, 2024 23:19 11s main
November 4, 2024 23:19 11s
Fix cell utilization report for place and route.
Lint #1117: Pull request #363 opened by grebe
November 4, 2024 19:55 11s grebe:fix_benchmark
November 4, 2024 19:55 11s
synth: Make synthesize_rtl emit a VerilogInfo provider
Lint #1116: Pull request #362 synchronize by QuantamHD
November 2, 2024 16:13 11s synthesis_verilog_info
November 2, 2024 16:13 11s
reformat bzl
Lint #1115: Commit 8548293 pushed by QuantamHD
November 2, 2024 16:13 13s synthesis_verilog_info
November 2, 2024 16:13 13s
October 16, 2024 20:06 18s