synth: Make synthesize_rtl emit a VerilogInfo provider #362
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Lets you do gate level sims easier if this rule can be passed as if it were a verilog_library Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
mikesinouye
approved these changes
Nov 7, 2024
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Lets you do gate level sims easier if this rule can be passed as if it were a verilog_library