[DCD_DWC2][ESP32P4][HS] Added cache synchronization (cont) #2883
Conversation
![github-advanced-security[bot]](https://avatars.githubusercontent.com/in/57789?s=60&v=4){kind=small}
| if (target STREQUAL esp32p4) | ||
| # P4 change alignment to 64 (DCache line size) for possible DMA configuration | ||
| list(APPEND compile_definitions | ||
| CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\) |
There was a problem hiding this comment.
CFG_TUSB_MEM_ALIGN will cause class driver to put correct aligment on usb/dma buffer.
There was a problem hiding this comment.
@roma-jam I just realized that we probably does not need the dma buffer to be 64 bytes aligned ? It only need to occupies the whole cache line (64 byte) right ? If you we can change it back to simply 4 bytes alignment.
PS: nevermind, I try to reduce alignment to 4 and it does not work, so 64 alignment is requierd
There was a problem hiding this comment.
Unfortunately the cache line size is configurable, and can be 64 or 128 bytes :(
This might be good enough for now, just so you keep this in mind if someone reports issues...
There was a problem hiding this comment.
what is the default value ? it isn't an problem at all. both the CFG_TUSB_MEM_ALIGN and CFG_TUD_MEM_DCACHE_LINE_SIZE is configurable at user level (tusb_config.h). So if use change it to 128, they shoud set this accordingly.
There was a problem hiding this comment.
default is 64. OK, great!
| #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 0 | ||
| #endif | ||
|
|
||
| #define CFG_TUD_MEM_DCACHE_ENABLE CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT |
There was a problem hiding this comment.
@HiFiPhile CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT is set to 1 when CFG_TUH_DWC2_DMA_ENABLE is enabled for required port such as P4. It is overwritable from tusb_config.h if user want to use MMU/PMA to make it non-cacheable.
| #endif | ||
|
|
||
| #ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE | ||
| #define CFG_TUD_MEM_DCACHE_LINE_SIZE 32 |
There was a problem hiding this comment.
should work with most ARM core like M7
| CFG_TUD_MEM_ALIGN union { | ||
| uint32_t setup_packet[2]; | ||
| #if CFG_TUD_MEM_DCACHE_ENABLE | ||
| uint8_t setup_packet_cache_padding[CFG_TUD_MEM_DCACHE_LINE_SIZE]; |
There was a problem hiding this comment.
@roma-jam we will need to do this to all buffered in the class driver, which may take a couple of follow-up PRs.
| TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top); | ||
| TU_ASSERT(_dcd_data.dfifo_top >= fifo_size + dwc2->grxfsiz); | ||
| _dcd_data.dfifo_top -= fifo_size; | ||
| // TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, dfifo_top); |
Check notice
Code scanning / CodeQL
Commented-out code Note
Describe the PR
Superceded #2877 since I need to make some modification to have
CFG_TUSB_MEM_ALIGN=__attribute__((aligned(64)))for p4 and add generic CFG for CFG_TUD_MEM_DCACHE_ENABLE/CFG_TUD_MEM_DCACHE_LINE_SIZE