Merge pull request #2883 from hathach/feature/esp32p4_dma_cache_syncr…

…onization

[DCD_DWC2][ESP32P4][HS] Added cache synchronization (cont)

hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt

@@ -15,6 +15,13 @@ list(APPEND compile_definitions
   BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
   )
 
+if (target STREQUAL esp32p4)
+  # P4 change alignment to 64 (DCache line size) for possible DMA configuration
+  list(APPEND compile_definitions
+    CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
+    )
+endif ()
+
 list(APPEND srcs
   # common
   ${tusb_src}/tusb.c
@@ -68,6 +75,7 @@ endif()
 idf_component_register(SRCS ${srcs}
   INCLUDE_DIRS ${tusb_src}
   REQUIRES src
+  PRIV_REQUIRES esp_mm
   )
 
 target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})

src/common/tusb_mcu.h

@@ -361,6 +361,18 @@
   #define TUP_USBIP_DWC2_ESP32
   #define TUP_RHPORT_HIGHSPEED    1  // port0 FS, port1 HS
   #define TUP_DCD_ENDPOINT_MAX    16 // FS 7 ep, HS 16 ep
+
+  #if defined(CFG_TUD_DWC2_DMA_ENABLE) && CFG_TUD_DWC2_DMA_ENABLE == 1
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  1
+  #endif
+
+  #if defined(CFG_TUH_DWC2_DMA_ENABLE) && CFG_TUH_DWC2_DMA_ENABLE == 1
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
+  #endif
+
+  #define CFG_TUD_MEM_DCACHE_LINE_SIZE  64
+  #define CFG_TUH_MEM_DCACHE_LINE_SIZE  64
+
   #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT  0 // TODO currently have issue with buffer DMA with espressif
 
 #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)

src/device/dcd.h

@@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) {
 
 // clean/flush data cache: write cache -> memory.
 // Required before an DMA TX transfer to make sure data is in memory
-void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+void dcd_dcache_clean(const void* addr, uint32_t data_size);
 
 // invalidate data cache: mark cache as invalid, next read will read from memory
 // Required BOTH before and after an DMA RX transfer
-void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+void dcd_dcache_invalidate(const void* addr, uint32_t data_size);
 
 // clean and invalidate data cache
 // Required before an DMA transfer where memory is both read/write by DMA
-void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);
 
 //--------------------------------------------------------------------+
 // Controller API

src/device/usbd.c

@@ -46,9 +46,7 @@
 // Weak stubs: invoked if no strong implementation is available
 //--------------------------------------------------------------------+
 TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
-  (void) rhport;
-  (void) eventid;
-  (void) in_isr;
+  (void) rhport; (void) eventid; (void) in_isr;
 }
 
 TU_ATTR_WEAK void tud_sof_cb(uint32_t frame_count) {
@@ -82,9 +80,7 @@ TU_ATTR_WEAK void tud_resume_cb(void) {
 }
 
 TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const* request) {
-  (void) rhport;
-  (void) stage;
-  (void) request;
+  (void) rhport; (void) stage; (void) request;
   return false;
 }
 
@@ -101,6 +97,18 @@ TU_ATTR_WEAK void dcd_disconnect(uint8_t rhport) {
   (void) rhport;
 }
 
+TU_ATTR_WEAK void dcd_dcache_clean(const void* addr, uint32_t data_size) {
+  (void) addr; (void) data_size;
+}
+
+TU_ATTR_WEAK void dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
+  (void) addr; (void) data_size;
+}
+
+TU_ATTR_WEAK void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
+  (void) addr; (void) data_size;
+}
+
 //--------------------------------------------------------------------+
 // Device Data
 //--------------------------------------------------------------------+