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[DCD_DWC2][ESP32P4][HS] Added cache synchronization (cont) #2883

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merged 5 commits into from
Nov 20, 2024
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[DCD_DWC2][ESP32P4][HS] Added cache synchronization (cont) #2883

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b8d31a5
feature(dcd_dwc2): Added cache synchronization
roma-jam Nov 19, 2024
43a45f2
feature(dcd_dwc2): Added cache synchronization
roma-jam Nov 19, 2024
4da5de7
have p4 dma somewhat working but having issue with buffer that does n…
hathach Nov 20, 2024
b3b8bd8
add CFG_TUD_MEM_DCACHE_ENABLE, CFG_TUD_MEM_DCACHE_LINE_SIZE option
hathach Nov 20, 2024
c61b55b
dcd wrap data to dcd_data_t, add padding for setup_packet to match ca…
hathach Nov 20, 2024
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8 changes: 8 additions & 0 deletions hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,13 @@ list(APPEND compile_definitions
BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
)

if (target STREQUAL esp32p4)
# P4 change alignment to 64 (DCache line size) for possible DMA configuration
list(APPEND compile_definitions
CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
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CFG_TUSB_MEM_ALIGN will cause class driver to put correct aligment on usb/dma buffer.

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@hathach hathach Nov 21, 2024 •
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@roma-jam I just realized that we probably does not need the dma buffer to be 64 bytes aligned ? It only need to occupies the whole cache line (64 byte) right ? If you we can change it back to simply 4 bytes alignment.

PS: nevermind, I try to reduce alignment to 4 and it does not work, so 64 alignment is requierd

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Unfortunately the cache line size is configurable, and can be 64 or 128 bytes :(
This might be good enough for now, just so you keep this in mind if someone reports issues...

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what is the default value ? it isn't an problem at all. both the CFG_TUSB_MEM_ALIGN and CFG_TUD_MEM_DCACHE_LINE_SIZE is configurable at user level (tusb_config.h). So if use change it to 128, they shoud set this accordingly.

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default is 64. OK, great!

)
endif ()

list(APPEND srcs
# common
${tusb_src}/tusb.c
Expand Down Expand Up @@ -68,6 +75,7 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${tusb_src}
REQUIRES src
PRIV_REQUIRES esp_mm
)

target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})
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12 changes: 12 additions & 0 deletions src/common/tusb_mcu.h
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Expand Up @@ -361,6 +361,18 @@
#define TUP_USBIP_DWC2_ESP32
#define TUP_RHPORT_HIGHSPEED 1 // port0 FS, port1 HS
#define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep

#if defined(CFG_TUD_DWC2_DMA_ENABLE) && CFG_TUD_DWC2_DMA_ENABLE == 1
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
#endif

#if defined(CFG_TUH_DWC2_DMA_ENABLE) && CFG_TUH_DWC2_DMA_ENABLE == 1
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
#endif

#define CFG_TUD_MEM_DCACHE_LINE_SIZE 64
#define CFG_TUH_MEM_DCACHE_LINE_SIZE 64

#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif

#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)
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6 changes: 3 additions & 3 deletions src/device/dcd.h
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Expand Up @@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) {

// clean/flush data cache: write cache -> memory.
// Required before an DMA TX transfer to make sure data is in memory
void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
void dcd_dcache_clean(const void* addr, uint32_t data_size);

// invalidate data cache: mark cache as invalid, next read will read from memory
// Required BOTH before and after an DMA RX transfer
void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
void dcd_dcache_invalidate(const void* addr, uint32_t data_size);

// clean and invalidate data cache
// Required before an DMA transfer where memory is both read/write by DMA
void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);

//--------------------------------------------------------------------+
// Controller API
Expand Down
20 changes: 14 additions & 6 deletions src/device/usbd.c
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Expand Up @@ -46,9 +46,7 @@
// Weak stubs: invoked if no strong implementation is available
//--------------------------------------------------------------------+
TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
(void) rhport;
(void) eventid;
(void) in_isr;
(void) rhport; (void) eventid; (void) in_isr;
}

TU_ATTR_WEAK void tud_sof_cb(uint32_t frame_count) {
Expand Down Expand Up @@ -82,9 +80,7 @@ TU_ATTR_WEAK void tud_resume_cb(void) {
}

TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const* request) {
(void) rhport;
(void) stage;
(void) request;
(void) rhport; (void) stage; (void) request;
return false;
}

Expand All @@ -101,6 +97,18 @@ TU_ATTR_WEAK void dcd_disconnect(uint8_t rhport) {
(void) rhport;
}

TU_ATTR_WEAK void dcd_dcache_clean(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
}

TU_ATTR_WEAK void dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
}

TU_ATTR_WEAK void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
}

//--------------------------------------------------------------------+
// Device Data
//--------------------------------------------------------------------+
Expand Down
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