Fdt x86 arm64

MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c

@@ -352,6 +352,9 @@ NvmeDisableController (
 
   for (Index = (Timeout * 500); Index != 0; --Index) {
     gBS->Stall (1000);
+    if (Index % 500 == 0) {
+      DEBUG ((DEBUG_INFO, "Please wait Index to be 0, Index/Max:(%d/%d)\n", Index, Timeout*500));
+    }
 
     //
     // Check if the controller is initialized

MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c

@@ -547,7 +547,7 @@ InitializePciHostBridge (
                    MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,
                    EFI_MEMORY_UC
                    );
-        ASSERT_EFI_ERROR (Status);
+        //ASSERT_EFI_ERROR (Status);
         Status = gDS->SetMemorySpaceAttributes (
                         HostAddress,
                         MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,
@@ -567,7 +567,7 @@ InitializePciHostBridge (
                           gImageHandle,
                           NULL
                           );
-          ASSERT_EFI_ERROR (Status);
+          //ASSERT_EFI_ERROR (Status);
         }
       }
     }
@@ -598,7 +598,7 @@ InitializePciHostBridge (
                     &HostBridge->ResAlloc,
                     NULL
                     );
-    ASSERT_EFI_ERROR (Status);
+    //ASSERT_EFI_ERROR (Status);
   }
 
   for (Link = GetFirstNode (&HostBridge->RootBridges)

UefiCpuPkg/CpuDxe/CpuDxe.inf

@@ -4,6 +4,7 @@
 #  Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>
 #  Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
 #  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#  Copyright (c) 2024, NewFW Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #

UefiCpuPkg/CpuDxeAArch64/AArch64Support.S

@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2024, NewFW Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+#include <AsmMacroLib.h>
+
+//UINTN
+//ArmGicV3GetControlRegister(
+//  VOID
+//  );
+ASM_FUNC(ArmGicV3GetControlRegister)
+        mrs     x0, icc_ctlr_el1
+        ret
+
+//VOID
+//ArmGicV3SetControlRegister(
+//  IN UINTN          Value
+//  );
+ASM_FUNC(ArmGicV3SetControlRegister)
+        msr     icc_ctlr_el1, x0
+        ret
+

UefiCpuPkg/CpuDxeAArch64/ArmCacheMaintenanceLib.c

@@ -0,0 +1,149 @@
+/** @file
+
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+  Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
+  Copyright (c) 2024, NewFW Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+STATIC
+VOID
+CacheRangeOperation (
+  IN  VOID            *Start,
+  IN  UINTN           Length,
+  IN  LINE_OPERATION  LineOperation,
+  IN  UINTN           LineLength
+  )
+{
+  UINTN  ArmCacheLineAlignmentMask;
+  // Align address (rounding down)
+  UINTN  AlignedAddress;
+  UINTN  EndAddress;
+
+  ArmCacheLineAlignmentMask = LineLength - 1;
+  AlignedAddress            = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
+  EndAddress                = (UINTN)Start + Length;
+
+  // Perform the line operation on an address in each cache line
+  while (AlignedAddress < EndAddress) {
+    LineOperation (AlignedAddress);
+    AlignedAddress += LineLength;
+  }
+
+  ArmDataSynchronizationBarrier ();
+}
+
+VOID
+EFIAPI
+InvalidateInstructionCache (
+  VOID
+  )
+{
+  ASSERT (FALSE);
+}
+
+VOID
+EFIAPI
+InvalidateDataCache (
+  VOID
+  )
+{
+  ASSERT (FALSE);
+}
+
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+  IN      VOID   *Address,
+  IN      UINTN  Length
+  )
+{
+  CacheRangeOperation (
+    Address,
+    Length,
+    ArmCleanDataCacheEntryToPoUByMVA,
+    ArmDataCacheLineLength ()
+    );
+  CacheRangeOperation (
+    Address,
+    Length,
+    ArmInvalidateInstructionCacheEntryToPoUByMVA,
+    ArmInstructionCacheLineLength ()
+    );
+
+  ArmInstructionSynchronizationBarrier ();
+
+  return Address;
+}
+
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+  VOID
+  )
+{
+  ASSERT (FALSE);
+}
+
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+  IN      VOID   *Address,
+  IN      UINTN  Length
+  )
+{
+  CacheRangeOperation (
+    Address,
+    Length,
+    ArmCleanInvalidateDataCacheEntryByMVA,
+    ArmDataCacheLineLength ()
+    );
+  return Address;
+}
+
+VOID
+EFIAPI
+WriteBackDataCache (
+  VOID
+  )
+{
+  ASSERT (FALSE);
+}
+
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+  IN      VOID   *Address,
+  IN      UINTN  Length
+  )
+{
+  CacheRangeOperation (
+    Address,
+    Length,
+    ArmCleanDataCacheEntryByMVA,
+    ArmDataCacheLineLength ()
+    );
+  return Address;
+}
+
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+  IN      VOID   *Address,
+  IN      UINTN  Length
+  )
+{
+  CacheRangeOperation (
+    Address,
+    Length,
+    ArmInvalidateDataCacheEntryByMVA,
+    ArmDataCacheLineLength ()
+    );
+  return Address;
+}

UefiCpuPkg/CpuDxeAArch64/ArmMmuLib.h

@@ -0,0 +1,74 @@
+/** @file
+
+  Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ARM_MMU_LIB_H_
+#define ARM_MMU_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+
+#include <Library/ArmLib.h>
+
+EFI_STATUS
+EFIAPI
+ArmConfigureMmu (
+  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
+  OUT VOID                          **TranslationTableBase OPTIONAL,
+  OUT UINTN                         *TranslationTableSize  OPTIONAL
+  );
+
+VOID
+EFIAPI
+ArmReplaceLiveTranslationEntry (
+  IN  UINT64   *Entry,
+  IN  UINT64   Value,
+  IN  UINT64   RegionStart,
+  IN  BOOLEAN  DisableMmu
+  );
+
+/**
+  Set the requested memory permission attributes on a region of memory.
+
+  BaseAddress and Length must be aligned to EFI_PAGE_SIZE.
+
+  If Attributes contains a memory type attribute (EFI_MEMORY_UC/WC/WT/WB), the
+  region is mapped according to this memory type, and additional memory
+  permission attributes (EFI_MEMORY_RP/RO/XP) are taken into account as well,
+  discarding any permission attributes that are currently set for the region.
+  AttributeMask is ignored in this case, and must be set to 0x0.
+
+  If Attributes contains only a combination of memory permission attributes
+  (EFI_MEMORY_RP/RO/XP), each page in the region will retain its existing
+  memory type, even if it is not uniformly set across the region. In this case,
+  AttributesMask may be set to a mask of permission attributes, and memory
+  permissions omitted from this mask will not be updated for any page in the
+  region. All attributes appearing in Attributes must appear in AttributeMask
+  as well. (Attributes & ~AttributeMask must produce 0x0)
+
+  @param[in]  BaseAddress     The physical address that is the start address of
+                              a memory region.
+  @param[in]  Length          The size in bytes of the memory region.
+  @param[in]  Attributes      Mask of memory attributes to set.
+  @param[in]  AttributeMask   Mask of memory attributes to take into account.
+
+  @retval EFI_SUCCESS           The attributes were set for the memory region.
+  @retval EFI_INVALID_PARAMETER BaseAddress or Length is not suitably aligned.
+                                Invalid combination of Attributes and
+                                AttributeMask.
+  @retval EFI_OUT_OF_RESOURCES  Requested attributes cannot be applied due to
+                                lack of system resources.
+
+**/
+EFI_STATUS
+ArmSetMemoryAttributes (
+  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN UINT64                Length,
+  IN UINT64                Attributes,
+  IN UINT64                AttributeMask
+  );
+
+#endif // ARM_MMU_LIB_H_