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Trying to make single-core SoC tutorial work for Nexys A7-100T
#205
opened Jul 26, 2023 by
HelpDesperatelyNeeded
Internal compiler error when trying to build risc-v toolchain for ariane processor
#204
opened Jul 25, 2023 by
HelpDesperatelyNeeded
How to change the clock frequency of a SoC prototyped on a xc7v2000t profpga
help wanted
Extra attention is needed
#182
opened Nov 14, 2022 by
LucaUrbinati44
Non-coherent DMA accelerator coherence mode doesn't work with Spandex Cache hierarchy
bug
Something isn't working
#172
opened Aug 10, 2022 by
jzuckerman
Missing "prebuilt" subfolder in Docker images for NVDLA third party accelerator
#168
opened Jul 18, 2022 by
JuanEsco063
Creating RTL for ASIC target
documentation
Improvements or additions to documentation
#152
opened Feb 25, 2022 by
yyhanafy
Support for additional boards
enhancement
New feature or request
#151
opened Feb 24, 2022 by
yyhanafy
Is Vivado Xsim supported as a simulator by ESP (could not find a script for it!)
enhancement
New feature or request
#139
opened Jan 13, 2022 by
yyhanafy
Support for additional boards
enhancement
New feature or request
#126
opened Sep 8, 2021 by
sanaallsanaall
Faulty reset of ESP and Spandex SystemC caches
bug
Something isn't working
#117
opened May 25, 2021 by
davide-giri
Automatic detection of enabled coherence models for accelerators
enhancement
New feature or request
#82
opened Nov 11, 2020 by
paulmnt
Support for additional platforms
enhancement
New feature or request
#68
opened Oct 29, 2020 by
JuanEsco063
Support Ariane w/ PMP
bug
Something isn't working
help wanted
Extra attention is needed
#65
opened Oct 1, 2020 by
paulmnt
C-based memory model for RTL simulation
bug
Something isn't working
enhancement
New feature or request
#30
opened Apr 2, 2020 by
paulmnt
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