Unexpected error when building design containing 3 CPU cores

[treble2]

Describe the bug
I run into the following error when building a design that has 3 CPU cores. I don't encounter this with designs that have 2 or 4 cores.

To Reproduce
Steps to reproduce the behavior:

1. In the directory for the vc707 board, use the ESP GUI to configure a 2x3 array that instantiates 3 Ibex CPU cores, a MEM tile, and an I/O tile
2. make vivado-syn

Expected behavior
Successful build without errors

Desktop:

• OS: ESP centos7-full docker image
• CAD tools versions: Xilinx Vivado 2023.2