Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add m-mode, s-mode interrupt test cases using test_model.h MSW and MTIMER clint macros. #435

Open
wants to merge 9 commits into
base: dev
Choose a base branch
from

Conversation

dansmathers
Copy link
Contributor

Description

Provide a detailed description of the changes performed by the PR.
This PR adds m-mode and s-mode interrupt test cases using clint MSW and MTIMER macros.

Related Issues

Please list all the issues related to this PR. Use NA if no issues exist
This pull requires using updates to riscv-config and riscof githubs:
riscv-software-src/riscv-config#169,
riscv-software-src/riscof#106

To include m-mode interrupt tests in riscof testlist flow, add Smclint to riscof yaml file, e.g.:
spike/spike_isa.yaml:
ISA: RV32IMCZicsr_Zifencei_Smclint

To include s-mode interrupt tests in riscof testlist flow, add Ssclint to riscof yaml file, e.g.:
spike/spike_isa.yaml:
ISA: RV32IMCZicsr_Zifencei_Ssclint

Ratified/Unratified Extensions

  • [X ] Ratified - This test just validates risc-v privilege spec interrupt behavior using clint MSW and MTIMER macros.
  • Unratified

List Extensions

List the extensions that your PR affects. In case of unratified extensions, please provide a link to the spec draft that was referred to make this PR.
N/A

Reference Model Used

  • [x ] SAIL
  • [ x] Spike
  • Other - < SPECIFY HERE >

Mandatory Checklist:

  • [x ] All tests are compliant with the test-format spec present in this repo ?

  • [x ] Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?

  • [x ] Ran the new tests on RISCOF in coverage mode

  • [x ] Link to Google-Drive folder containing the new coverage reports (See this for more info):
    I had issues with coverage. As you can see in the coverage report, no coverage points on any existing or new tests hit.

  • https://drive.google.com/drive/folders/153nIRznXwzu7N1rWl9CesqwAXLqwHoEx

  • Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE > ???

  • Changelog entry created with a minor patch

Optional Checklist:

  • RISCV-V CTG PR link if tests were generated using it : < SPECIFY HERE >
  • Were the tests hand-written/modified ? No, automated.
  • [x ] Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
  • [N/A ] If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

…ation

M-mode interrupt test-cases using msw and mtimer clint interrupts

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
requires 
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106

To include these tests in riscof testlist flow, add Smclint to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclint



Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
Coverage checks mcause.int to verify if an interrupt occurred

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
Description of s-mode interrupt testcases

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
s-mode interrupt testcases by delegating CLINT MSW/MTIMER interrupts

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants