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@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture
README.md

Welcome to the RISC-V Non-ISA Specifications 👋

RISC-V Logo

Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.4k 238

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    Python 715 165

  3. riscv-arch-test riscv-arch-test Public

    Assembly 517 204

  4. riscv-sbi-doc riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    Makefile 354 91

  5. rvv-intrinsic-doc rvv-intrinsic-doc Public

    C 298 89

  6. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 165 47

Repositories

Showing 10 of 35 repositories
  • riscv-ap-tee-io Public

    This TG will define AP-TEE-IO ABI extensions to provide Confidential VM-assigned devices with secure direct access to confidential memory as well as MMIO, removing the dependence on para-virtualized I/O.

    riscv-non-isa/riscv-ap-tee-io’s past year of commit activity
    Makefile 10 CC-BY-4.0 4 8 0 Updated Nov 26, 2024
  • riscv-security-model Public

    RISC-V Security Model

    riscv-non-isa/riscv-security-model’s past year of commit activity
    Makefile 29 CC-BY-4.0 14 3 0 Updated Nov 25, 2024
  • riscv-trace-spec Public

    RISC-V Processor Trace Specification

    riscv-non-isa/riscv-trace-spec’s past year of commit activity
    C 165 CC-BY-4.0 47 23 12 Updated Nov 25, 2024
  • iopmp-spec Public

    This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

    riscv-non-isa/iopmp-spec’s past year of commit activity
    Makefile 15 CC-BY-4.0 4 5 0 Updated Nov 25, 2024
  • riscv-external-debug-security Public

    The RISC-V External Debug Security Specification

    riscv-non-isa/riscv-external-debug-security’s past year of commit activity
    Makefile 19 CC-BY-4.0 2 2 1 Updated Nov 25, 2024
  • riscv-acpi-rimt Public

    RISC-V ACPI I/O Mapping Table Specification

    riscv-non-isa/riscv-acpi-rimt’s past year of commit activity
    Makefile 2 CC-BY-4.0 2 0 1 Updated Nov 22, 2024
  • tg-nexus-trace Public

    RISC-V Nexus Trace TG documentation and reference code

    riscv-non-isa/tg-nexus-trace’s past year of commit activity
    C 44 CC-BY-4.0 33 5 0 Updated Nov 22, 2024
  • riscv-c-api-doc Public

    Documentation of the RISC-V C API

    riscv-non-isa/riscv-c-api-doc’s past year of commit activity
    Makefile 75 CC-BY-4.0 41 17 11 Updated Nov 21, 2024
  • riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    riscv-non-isa/riscv-asm-manual’s past year of commit activity
    Makefile 1,447 CC-BY-4.0 238 9 9 Updated Nov 21, 2024
  • riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    riscv-non-isa/riscv-elf-psabi-doc’s past year of commit activity
    Python 715 CC-BY-4.0 165 55 26 Updated Nov 21, 2024
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