- Microprocessor-Without-Interlocked-Pipeline-Stages-MIPS
Photo by Michael Dziedzic on Unsplash
RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.
- Interrupt allowed.
- Pipeline structure.
- Unconditional or Conditional jumps, both are allowed.
- Architecture: 8 Bits
- Total stages: 5
- Instruction set: 24 Bit
- Input / Output pins: 21
- Frequency: 585 MHz (100 MHz on Artix-07)
- CPI: 1.25
- Data memory: 8 Width, 256 Depth
- Program Memory: 24 Width, 256 Depth
- Opcodes: 28
- Total interrupts: 1
- Registers: 32
- Address: 8 Bits
- Total flags: 4
- flag[0]= carry
- flag[1]= zero
- flag[2]= overflow
- flag[3]= parity
- Register bank size: 32*8 bits
- Instruction formats: 7
- Total types of jumps: 5
- Conditional: 4
- Unconditional: 1
- An arithmetic logic unit (ALU) is a digital electronic circuit that performs arithmetic and bitwise logical operations on integer binary numbers.
- An ALU is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers and graphics processing units (GPUs).
- A single CPU or GPU may contain multiple ALUs.
- The inputs to an ALU are the data to be operated on, called operands; and an opcode (operation code) indicating the operation to be performed; the ALU's output is the result of the performed operation.
- In many designs, the ALU also exchanges additional information with a status register (flag), which relates to the result of the current or previous operations.
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The executon block fetches instructions from the queue, decodes the instructions and executes the arithmetic-logical operations using the ALU block.
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Note:
- Arithmetic operations are on 2's complemented numbers.
- 'reset' is negative level triggered and clock synchronous.
- Execution Block Simulation Results:
- Generates instructions for decode, execution, and data memory blocks.
- Takes care of different controls.
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There are 3 different 2 x 1 multiplexer having selection line namely ‘Stall’, ‘pc_mux_sel’ and ‘Stall_pm’ respectively.
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‘Stall’ generated from ‘stall control’ block (i.e. one of the module of processor) which is used to select assign either Hold_Address or Next_Address as CAJ.
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‘pc_mux_sel’ decides whether current address will pass to program memory or address provided by ‘jump control’ block.
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A mux with ‘Stall_pm’ selection bit decides whether to pass actual instruction (PM_out) or pass previous instruction (ins_prv) to ‘ins_pm’.
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Another two multiplexers with ‘reset’ selection bit are used to reset ‘Current_Address’ and ‘ins’ values.
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Processor needs to generate new instruction at every positive edge of clock and ‘program counter’ will provide address of the new instruction.
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Program counter is combination of ‘increment’ (+) and ‘register’ block.
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‘Increment’ block increments address and register will pass that value to ‘Next_Address’ on every positive edge of the clock and when there is reset it will clear the output of ‘register’.
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Another important block is program memory which has been designed using Xilinx IP core generator.
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Program Counter and Instruction Memory Block Simulation Results:
- Note:
- The memory data for each address can be written in the COE file. The COE file can be generated using Xilinx ISE. The ROM_data.txt is present in the repository.
- For more details click here.
- This block generates operands (A and B) for Execution block based on the instruction generated from Instruction Memory block.
- Instruction bits 13 to 9 are used as first operand (A) address and 8 to 4 are used as second operand (B) address.
- If applied instruction is register type then both the operands are fetched from register bank, else one operand (A) is fetched from register bank and other operand (B) is taken as an immediate number (imm).
- This selection is controled by 2x1 Mux.
- Data forwarding operations are performed by both 4x1 Mux based on the values applied to it’s selection line (mux_sel_A and mux_sel_B).
- Answer from Data Memory block (ans_dm) is written in register bank as per the address indicated by RW_dm.
- Register Bank Simulation Results:
- Data Memory is designed using IP core.
- It’s a 256x8 RAM with R/W and enable signal.
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Data read or write in Data Memory is possible only if ‘mem_en_ex’ signal is
- If ‘mem_rw_ex’ is 0 data read operation will perform else data write.
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Data written in the Data Memory should be provided to ‘DM_data’; and ‘ans_ex’ is used as an address.
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2x1 Mux is used to select between execution block answer (Ex_out) or Data Memory’s output (DM_out).
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When ‘mem_mux_sel_dm’ is 1, it will select ‘DM_out’ as an ‘ans_dm’ else it will select ‘Ex_out’ as an ‘ans_dm’.
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Data Memory Block Simulation Results:
- Some instructions like ‘Load’ and ‘Conditional Jump’ will create control hazard in pipeline processor.
- To overcome this problem, we need to stall pipeline for one or two clock cycles.
- Stall Control block decides when to stall a pipeline.
- Also, this block will stall pipeline forever when ‘HLT’ instruction will execute.
Stall Control Block Simulation Results:
- Write Back block is used to delay ‘ans_dm’ for one clock cycle.
- This block helps to resolve read after write hazard in the IDOF (Instruction Decode and Operand Fetch) stage.
- Jump control block generates jump location address (jmp_loc) and mux control signal (pc_mux_sel) for program memory block, based on jump conditions and value of interrupt.
- For conditional jumps (JC, JNC, JZ and JNZ), if condition is true then ‘pc_mux_sel’ value will be ‘1’, else we check for unconditional jump (JMP), interrupt and return (RET) instructions, if any of these instruction/signal is true then also ‘pc_mux_sel’ value will be ‘1’, for other cases ‘pc_mux_sel’ value will be ‘0’.
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When interrupt signal value is ‘1’, we stores ‘current_address’ and ‘flag_ex’ in the system and program will jump to interrupt subroutine location (8’hF0).
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When interrupt subroutine is over then we provide RET instruction to continue our main program, for that we need to reproduc ‘current_address’ and ‘flag_ex’ which was previously stored in system.
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Jump Control Block Simulation Results:
- Dependency check block handles data hazard in pipeline processor.
- It can check dependency of current instruction with previous three instructions and enables data forwarding in pipeline by generating ‘mux_sel_A’ and ‘mux_sel_B’ signals.
- This block is also generates memory control and immediate control signals. All outputs of this block are generated at the positive edge of clock.
- Dependency Check Block Simulation Results:
- Addition
- Multiplication
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Upload the mainmodule.bit file on Nexys A7: FPGA.
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Download the repository. Open the project in Xilinx ISE and simulate the mainmodule_tb.v file.
Any contributions you make are greatly appreciated.
- Fork the Project
- Create your Feature Branch (
git checkout -b feature/amazing-feature) - Commit your Changes (
git commit -m 'feat: some amazing feature') - Push to the Branch (
git push origin feature/amazing-feature) - Open a Pull Request
Distributed under the MIT License. See LICENSE for more information.
