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MainModule_summary.html
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>MainModule Project Status (11/03/2017 - 15:30:31)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>PROCESSORS.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>MainModule</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Placed and Routed</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc7a100t-1csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD> </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD> </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule.unroutes'>All Signals Completely Routed</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>0 <A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>147</TD>
<TD ALIGN=RIGHT>126,800</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>147</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>360</TD>
<TD ALIGN=RIGHT>63,400</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
<TD ALIGN=RIGHT>347</TD>
<TD ALIGN=RIGHT>63,400</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
<TD ALIGN=RIGHT>312</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
<TD ALIGN=RIGHT>35</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD>
<TD ALIGN=RIGHT>12</TD>
<TD ALIGN=RIGHT>19,000</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Dual Port RAM</TD>
<TD ALIGN=RIGHT>12</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
<TD ALIGN=RIGHT>12</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Single Port RAM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Shift Register</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>1</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD>
<TD ALIGN=RIGHT>1</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>110</TD>
<TD ALIGN=RIGHT>15,850</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>365</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>240</TD>
<TD ALIGN=RIGHT>365</TD>
<TD ALIGN=RIGHT>65%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
<TD ALIGN=RIGHT>5</TD>
<TD ALIGN=RIGHT>365</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>120</TD>
<TD ALIGN=RIGHT>365</TD>
<TD ALIGN=RIGHT>32%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
<TD ALIGN=RIGHT>6</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD>
<TD ALIGN=RIGHT>21</TD>
<TD ALIGN=RIGHT>126,800</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>19</TD>
<TD ALIGN=RIGHT>210</TD>
<TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of LOCed IOBs</TD>
<TD ALIGN=RIGHT>19</TD>
<TD ALIGN=RIGHT>19</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB36E1/FIFO36E1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>135</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB18E1/FIFO18E1s</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>270</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using RAMB18E1 only</TD>
<TD ALIGN=RIGHT>2</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using FIFO18E1 only</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGCTRLs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGCTRLs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IDELAYE2/IDELAYE2_FINEDELAYs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>300</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGICE2/ILOGICE3/ISERDESE2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>300</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ODELAYE2/ODELAYE2_FINEDELAYs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGICE2/OLOGICE3/OSERDESE2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>300</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PHASER_IN/PHASER_IN_PHYs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PHASER_OUT/PHASER_OUT_PHYs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHCEs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>96</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFRs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of CAPTUREs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DNA_PORTs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48E1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>240</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of EFUSE_USRs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of FRAME_ECCs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IBUFDS_GTE2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IDELAYCTRLs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>6</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IN_FIFOs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MMCME2_ADVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>6</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OUT_FIFOs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCIE_2_1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PHASER_REFs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>6</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PHY_CONTROLs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>6</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLLE2_ADVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>6</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of XADCs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>3.98</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
</TABLE>
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
<A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B> </B></TD>
<TD COLSPAN='2'> </TD>
</TABLE>
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Nov 8 19:07:33 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\_xmsgs/xst.xmsgs?&DataKey=Warning'>55 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\_xmsgs/xst.xmsgs?&DataKey=Info'>18 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Nov 8 19:07:52 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Nov 8 19:09:29 2017</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Nov 8 19:10:08 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\_xmsgs/par.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Nov 8 19:10:33 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\MainModule.bgn'>Bitgen Report</A></TD><TD>Out of Date</TD><TD>Fri Nov 3 19:24:08 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>2 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\_xmsgs/bitgen.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
</TABLE>
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Nov 8 19:21:46 2017</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\netgen/synthesis/MainModule_synthesis.nlf'>Post-Synthesis Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Nov 2 19:49:48 2017</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\netgen/par/MainModule_timesim.nlf'>Post-Place and Route Simulation Model Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Nov 8 19:11:09 2017</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri Nov 3 19:24:09 2017</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Jay Patel/Downloads/PROCESSORS-20171102T120455Z-001/PROCESSORS\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri Nov 3 19:24:15 2017</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 11/09/2017 - 14:02:14</center>
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