Merge pull request #40 from DylanVanAssche/feature/ISSUE-39

Total testbench fixed #39

receiver/access/access.vhd

@@ -14,7 +14,7 @@
 --3)Inputs:
 -- sdi_spread, pn_select, rst, clk, clk_en
 --4)Outputs:
--- bitsample, databit
+-- bitsample_out, databit
 --**********************
 --* LIBRARIES & ENTITY *
 --**********************
@@ -37,6 +37,7 @@ ARCHITECTURE behavior OF access_layer IS
 	SIGNAL chipsample_2	: std_logic := '1';
 	SIGNAL chipsample_3	: std_logic := '1';
 	SIGNAL bitsample	: std_logic := '0';
+	SIGNAL bitsample_edged	: std_logic := '0';
 	SIGNAL matchfilter_out	: std_logic := '0';
 	SIGNAL despreader_out	: std_logic := '0';
 	SIGNAL seq_det		: std_logic := '0';
@@ -48,7 +49,7 @@ ARCHITECTURE behavior OF access_layer IS
 	SIGNAL extb		: std_logic := '0';
 BEGIN
 -- Connect signals to outputs
-bitsample_out <= bitsample;
+bitsample_out <= bitsample_edged;
 -- Access layer parts
 dpll : ENTITY work.dpll(behavior)
 PORT MAP
@@ -96,6 +97,17 @@ PORT MAP
 	pn_2       => pn_2,
 	pn_3       => pn_3
 );
+-- PNgenerator depends on chipsample which causes the bitsample to be too long for the datalink's shiftregister.
+-- The bitsample signal is reduced to the length of the clk_en period to avoid issues using an edgedetector.
+edgedetector_bitsample : ENTITY work.edgedetector(behavior) 
+PORT MAP
+(
+	data   => bitsample,
+	puls   => bitsample_edged,
+	clk    => clk,
+	clk_en => clk_en,
+	rst    => rst
+);
 mux_pn_despread : ENTITY work.mux(behavior)
 PORT MAP
 (
@@ -134,7 +146,7 @@ PORT MAP
 	clk_en       => clk_en,
 	rst          => rst,
 	chipsample   => chipsample_3,
-	bitsample    => bitsample,
+	bitsample    => bitsample_edged,
 	sdi_despread => sdi_despread,
 	databit      => databit
 );

receiver/access/dpll/dpll_samplecounter.vhd

@@ -42,17 +42,17 @@ END dpll_samplecounter;
 --*********************************************
 ARCHITECTURE behavior OF dpll_samplecounter IS
 	-- Segment codes for decoder
-	CONSTANT SEG_A			: std_logic_vector(4 DOWNTO 0) := "10000";
-	CONSTANT SEG_B			: std_logic_vector(4 DOWNTO 0) := "01000";
-	CONSTANT SEG_C			: std_logic_vector(4 DOWNTO 0) := "00100";
-	CONSTANT SEG_D			: std_logic_vector(4 DOWNTO 0) := "00010";
-	CONSTANT SEG_E			: std_logic_vector(4 DOWNTO 0) := "00001";
+	CONSTANT SEG_A      		: std_logic_vector(4 DOWNTO 0) := "10000";
+	CONSTANT SEG_B      		: std_logic_vector(4 DOWNTO 0) := "01000";
+	CONSTANT SEG_C      		: std_logic_vector(4 DOWNTO 0) := "00100";
+	CONSTANT SEG_D      		: std_logic_vector(4 DOWNTO 0) := "00010";
+	CONSTANT SEG_E      		: std_logic_vector(4 DOWNTO 0) := "00001";
 	-- Reset values for the downcounter for each segment
-	CONSTANT SEG_A_RST_VALUE	: std_logic_vector(4 DOWNTO 0) := "01001";
-	CONSTANT SEG_B_RST_VALUE	: std_logic_vector(4 DOWNTO 0) := "10001";
-	CONSTANT SEG_C_RST_VALUE	: std_logic_vector(4 DOWNTO 0) := "00101";
-	CONSTANT SEG_D_RST_VALUE	: std_logic_vector(4 DOWNTO 0) := "00011";
-	CONSTANT SEG_E_RST_VALUE	: std_logic_vector(4 DOWNTO 0) := "10101";
+	CONSTANT SEG_A_RST_VALUE	: std_logic_vector(4 DOWNTO 0) := "10010"; --way too early: 18
+	CONSTANT SEG_B_RST_VALUE	: std_logic_vector(4 DOWNTO 0) := "10000"; --too early: 16
+	CONSTANT SEG_C_RST_VALUE	: std_logic_vector(4 DOWNTO 0) := "01111"; --ok: 15
+	CONSTANT SEG_D_RST_VALUE	: std_logic_vector(4 DOWNTO 0) := "00011"; --too late: 14
+	CONSTANT SEG_E_RST_VALUE	: std_logic_vector(4 DOWNTO 0) := "01110"; --way too late: 12
 	-- Downcounter
 	SIGNAL n_count			: std_logic_vector(4 DOWNTO 0);
 	SIGNAL p_count			: std_logic_vector(4 DOWNTO 0);

receiver/access/edgedetector/edgedetector.vhd

@@ -0,0 +1,72 @@
+--***********************************************
+--* TITLE: Edgedetector FSM (transmitter)	*
+--* TYPE: Component 				*
+--* AUTHOR: Dylan Van Assche 			*
+--* DATE: 05/10/2017 				*
+--***********************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Check if a signal goes from LOW to HIGH
+--2)Principle:
+-- Moore FSM
+--3)Inputs:
+-- data, clk, clk_en, rst
+--4)Outputs:
+-- puls
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+ENTITY edgedetector IS
+	PORT
+	(
+		data   : IN std_logic;
+		clk    : IN std_logic;
+		clk_en : IN std_logic;
+		rst    : IN std_logic;
+		puls   : OUT std_logic
+	);
+END edgedetector;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE behavior OF edgedetector IS
+	TYPE state IS (s0, s1, s2);
+	SIGNAL present_state, next_state : state;
+BEGIN
+-- 2-Process: synchronous part
+sync_moore : PROCESS (clk)
+BEGIN
+	IF (rising_edge(clk) AND clk_en = '1') THEN
+		IF (rst = '1') THEN -- reset line high, go to initial state
+			present_state <= s0;
+		ELSE -- normal operation
+			present_state <= next_state;
+		END IF;
+	END IF;
+END PROCESS sync_moore;
+-- 2-Process: combinatoric part
+comb_moore : PROCESS (present_state, data)
+BEGIN
+	CASE present_state IS
+		WHEN s0 => puls <= '0'; -- Initial state
+		IF (data = '1') THEN -- data high, send puls
+			next_state <= s1;
+		ELSE
+			next_state <= s0;
+		END IF;
+		WHEN s1 => puls <= '1'; -- Send puls out (high)
+		next_state      <= s2;
+		WHEN s2 => puls <= '0'; -- After 1 CLK cycle, puls low
+		IF (data = '0') THEN -- data low, go to initial state
+			next_state <= s0;
+		ELSE
+			next_state <= s2;
+		END IF;
+	END CASE;
+END PROCESS comb_moore;
+END behavior;

receiver/access/edgedetector/edgedetector_test.vhd

@@ -0,0 +1,95 @@
+--*******************************************************
+--* TITLE: Edgedetector FSM TESTBENCH (transmitter)	*
+--* TYPE: Component 					*
+--* AUTHOR: Dylan Van Assche 				*
+--* DATE: 05/10/2017 					*
+--*******************************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Check if a signal goes from LOW to HIGH
+--2)Principle:
+-- Moore FSM
+--3)Inputs:
+-- data, clk, clk_en, rst
+--4)Outputs:
+-- puls
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+ENTITY edgedetector_test IS
+END edgedetector_test;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE structural OF edgedetector_test IS
+	--initialize signals & constants
+	CONSTANT period   : TIME := 100 ns;
+	CONSTANT delay    : TIME := 10 ns;
+	SIGNAL end_of_sim : BOOLEAN := false;
+	SIGNAL data       : std_logic;
+	SIGNAL clk        : std_logic;
+	SIGNAL clk_en     : std_logic := '1';
+	SIGNAL rst        : std_logic;
+	SIGNAL puls       : std_logic;
+BEGIN
+--***********
+--* MAPPING *
+--***********
+-- Connect ports to signals (PORT => SIGNAL)
+uut : ENTITY work.edgedetector(behavior)
+	PORT MAP
+	(
+		data   => data,
+		puls   => puls,
+		clk    => clk,
+		clk_en => clk_en,
+		rst    => rst
+	);
+
+-- Only for synchronous components
+clock : PROCESS
+	BEGIN
+	clk <= '0';
+	WAIT FOR period/2;
+	LOOP
+		clk <= '0';
+		WAIT FOR period/2;
+		clk <= '1';
+		WAIT FOR period/2;
+	EXIT WHEN end_of_sim;
+	END LOOP;
+	WAIT;
+END PROCESS clock;
+-- Testbench
+PROCESS
+	-- Reset procedure to initialize the component
+	PROCEDURE reset IS
+	BEGIN
+		rst <= '1';
+		WAIT FOR period * 2;
+		rst <= '0';
+		WAIT FOR period;
+	END reset;
+	-- Test data procedure
+	PROCEDURE test (CONSTANT testdata : IN std_logic) IS
+	BEGIN
+		data <= testdata;
+		WAIT FOR period * 4;
+		END test;
+BEGIN
+	-- Reset at startup
+	reset;
+	-- Test data
+	test('0');
+	test('1');
+	test('0');
+	test('1');
+	end_of_sim <= true;
+	WAIT;
+END PROCESS;
+END structural;

receiver/access/pngenerator/pngenerator.vhd

@@ -74,7 +74,7 @@ BEGIN
 	END IF;
 END PROCESS pn_sync;
 -- 2-Process: combinatoric part
-pn_comb : PROCESS (shdata1, shdata2, linear_feedback1, linear_feedback2, seq_det)
+pn_comb : PROCESS (shdata1, shdata2, linear_feedback1, linear_feedback2, seq_det, full_seq)
 BEGIN
 	IF (seq_det = '1') THEN
 		shdata1_next <= "00010";

receiver/application/datalatch/datalatch.vhd

@@ -38,8 +38,8 @@ END datalatch;
 --* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
 --*********************************************
 ARCHITECTURE behavior OF datalatch IS
-	SIGNAL latch: std_logic_vector(3 DOWNTO 0);
-	SIGNAL latch_next: std_logic_vector(3 DOWNTO 0);
+	SIGNAL latch: std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
+	SIGNAL latch_next: std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
 	CONSTANT PREAMBLE_VALUE: std_logic_vector(6 DOWNTO 0) := "0111110";
 BEGIN
 -- connect signal to output

receiver/datalink/datashiftreg/datashiftreg.vhd

@@ -36,7 +36,7 @@ END;
 --* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
 --*********************************************
 ARCHITECTURE behavior OF datashiftreg IS
-	SIGNAL shdata          : std_logic_vector(10 DOWNTO 0);
+	SIGNAL shdata          : std_logic_vector(10 DOWNTO 0) := (OTHERS => '0');
 	SIGNAL shdata_next     : std_logic_vector(10 DOWNTO 0) := (OTHERS => '0');
 BEGIN
 -- connect signals to outputs

receiver/nco.vhd

@@ -0,0 +1,66 @@
+--***************************************
+--* TITLE: NCO (receiver)		*
+--* TYPE: Component 			*
+--* AUTHOR: Dylan Van Assche 		*
+--* DATE: 13/12/2017 			*
+--***************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- NCO to divide the 100 Mhz clock of the Virtex II Pro.
+--2)Principle:
+-- When counting down, send a clk_en signal out and restart.
+--3)Ingangen:
+-- rst, clk
+--4)Uitgangen:
+-- clk_en
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+ENTITY nco_rx IS
+	PORT
+	(
+		clk     : IN std_logic;
+		rst     : IN std_logic;
+		clk_en  : OUT std_logic
+	);
+END;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE behavior OF nco_rx IS
+	SIGNAL n_count		: std_logic_vector(1 DOWNTO 0);
+	SIGNAL p_count		: std_logic_vector(1 DOWNTO 0);
+	SIGNAL enable		: std_logic := '1'; -- allow for reset
+	SIGNAL enable_next	: std_logic := '0';
+	CONSTANT TRIGGER	: std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
+BEGIN
+clk_en <= enable;
+-- 2-Process: synchronous part
+count_sync : PROCESS (clk)
+BEGIN
+	IF (rising_edge(clk)) THEN
+		IF (rst = '1') THEN -- rst line high, go to initial state
+			p_count <= (OTHERS => '0');
+			enable <= '1';
+		ELSE -- normal operation
+			p_count <= n_count;
+			enable <= enable_next;
+		END IF;
+	END IF;
+END PROCESS count_sync;
+-- 2-Process: combinatoric part
+count_comb : PROCESS (p_count, enable)
+BEGIN
+	n_count <= p_count + 1;
+	IF (n_count = TRIGGER) THEN -- clk_en signal
+		enable_next <= '1';
+	ELSE
+		enable_next <= '0';
+	END IF;
+END PROCESS count_comb;
+END behavior;