Merge pull request #38 from DylanVanAssche/feature/ISSUE-28

Receiver top file

receiver/access/access.vhd

@@ -33,19 +33,19 @@ ENTITY access_layer IS
 	);
 END access_layer;
 ARCHITECTURE behavior OF access_layer IS
-	SIGNAL chipsample_1	: std_logic;
-	SIGNAL chipsample_2	: std_logic;
-	SIGNAL chipsample_3	: std_logic;
-	SIGNAL bitsample	: std_logic;
-	SIGNAL matchfilter_out	: std_logic;
-	SIGNAL despreader_out	: std_logic;
-	SIGNAL seq_det		: std_logic;
-	SIGNAL pn_1		: std_logic;
-	SIGNAL pn_2		: std_logic;
-	SIGNAL pn_3		: std_logic;
-	SIGNAL pn_seq		: std_logic;
-	SIGNAL sdi_despread	: std_logic;
-	SIGNAL extb		: std_logic;
+	SIGNAL chipsample_1	: std_logic := '1';
+	SIGNAL chipsample_2	: std_logic := '1';
+	SIGNAL chipsample_3	: std_logic := '1';
+	SIGNAL bitsample	: std_logic := '0';
+	SIGNAL matchfilter_out	: std_logic := '0';
+	SIGNAL despreader_out	: std_logic := '0';
+	SIGNAL seq_det		: std_logic := '0';
+	SIGNAL pn_1		: std_logic := '0';
+	SIGNAL pn_2		: std_logic := '0';
+	SIGNAL pn_3		: std_logic := '0';
+	SIGNAL pn_seq		: std_logic := '0';
+	SIGNAL sdi_despread	: std_logic := '0';
+	SIGNAL extb		: std_logic := '0';
 BEGIN
 -- Connect signals to outputs
 bitsample_out <= bitsample;
@@ -59,7 +59,8 @@ PORT MAP
 	sdi_spread	=> sdi_spread,
 	chipsample_1	=> chipsample_1,
 	chipsample_2	=> chipsample_2,
-	chipsample_3	=> chipsample_3
+	chipsample_3	=> chipsample_3,
+	extb_out	=> extb
 );
 matchfilter : ENTITY work.matchfilter(behavior)
 PORT MAP

receiver/access/correlator/correlator.vhd

@@ -74,8 +74,10 @@ BEGIN
 	-- load dataregister on bitsample with counter value
 	IF (bitsample = '1' AND p_count(5) = '1' ) THEN --MSB = 1 then at least 32 or higher
 		n_reg <= '1';
+		n_count <= "100000"; -- reset to 32
 	ELSIF (bitsample = '1' AND p_count(5) = '0' ) THEN --MSB = 0 then at max 31 or lower
 		n_reg <= '0';
+		n_count <= "100000"; -- reset to 32
 	ELSE -- all other cases, do nothing
 		n_reg <= p_reg;
 	END IF;

receiver/access/correlator/correlator_test.vhd

@@ -96,11 +96,14 @@ BEGIN
 		test('0', '1', '1');
 	END LOOP;
 	test('1', '0', '0'); -- show databit
-
-	FOR i IN 0 TO 60 LOOP
+	test('0', '0', '0'); -- wait
+	WAIT FOR PERIOD*3;
+	FOR i IN 0 TO 30 LOOP
 		test('0', '1', '0');
 	END LOOP;
 	test('1', '0', '0'); -- show databit
+	test('0', '0', '0'); -- wait
+	WAIT FOR PERIOD*3;
 	-- Nothing may happen now:
 	clk_en <= '0';
 	test('0', '1', '0');

receiver/access/despreading/despread.vhd

@@ -23,7 +23,7 @@ USE ieee.std_logic_1164.ALL;
 USE ieee.std_logic_unsigned.ALL;
 
 ENTITY despreader IS
-  PORT (
+	PORT (
 		clk          : IN  std_logic;
 		clk_en       : IN  std_logic;
 		rst          : IN  std_logic;
@@ -38,8 +38,8 @@ END despreader;
 --* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
 --*********************************************
 ARCHITECTURE behavior OF despreader IS
-	SIGNAL despread: std_logic;
-	SIGNAL despread_next: std_logic;
+	SIGNAL despread		: std_logic := '0';
+	SIGNAL despread_next	: std_logic;
 BEGIN
 -- connect signal to output
 sdi_despread <= despread;

receiver/access/pngenerator/pngenerator.vhd

@@ -41,14 +41,14 @@ END;
 --* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
 --*********************************************
 ARCHITECTURE behavior OF pngenerator IS
-	SIGNAL shdata1          : std_logic_vector(4 DOWNTO 0);
+	SIGNAL shdata1          : std_logic_vector(4 DOWNTO 0) := "00010";
 	SIGNAL shdata1_next     : std_logic_vector(4 DOWNTO 0) := (OTHERS => '0');
-	SIGNAL shdata2          : std_logic_vector(4 DOWNTO 0);
+	SIGNAL shdata2          : std_logic_vector(4 DOWNTO 0) := "00111";
 	SIGNAL shdata2_next     : std_logic_vector(4 DOWNTO 0) := (OTHERS => '0');
 	SIGNAL full_seq_next    : std_logic;
-	SIGNAL full_seq         : std_logic;
-	SIGNAL linear_feedback1 : std_logic;
-	SIGNAL linear_feedback2 : std_logic;
+	SIGNAL full_seq         : std_logic := '0';
+	SIGNAL linear_feedback1 : std_logic := '0';
+	SIGNAL linear_feedback2 : std_logic := '0';
 BEGIN
 -- calculate linear feedback for both PN counters (LFSR)
 linear_feedback1 <= (shdata1(0) XOR shdata1(3));

receiver/application/application_test.vhd

@@ -29,8 +29,8 @@ END application_layer_test;
 --*********************************************
 ARCHITECTURE structural OF application_layer_test IS
 	--initialize signals & constants
-	CONSTANT PERIOD        : TIME := 100 ns;
-	CONSTANT DELAY         : TIME := 10 ns;
+	CONSTANT period        : TIME := 100 ns;
+	CONSTANT delay         : TIME := 10 ns;
 	SIGNAL end_of_sim      : BOOLEAN := false;
 	SIGNAL clk             : std_logic := '0';
 	SIGNAL clk_en          : std_logic := '1';
@@ -59,12 +59,12 @@ uut : ENTITY work.application_layer(behavior)
 clock : PROCESS
 BEGIN
 	clk <= '0';
-	WAIT FOR PERIOD/2;
+	WAIT FOR period/2;
 	LOOP
 		clk <= '0';
-		WAIT FOR PERIOD/2;
+		WAIT FOR period/2;
 		clk <= '1';
-		WAIT FOR PERIOD/2;
+		WAIT FOR period/2;
 		EXIT WHEN end_of_sim;
 	END LOOP;
 	WAIT;
@@ -75,9 +75,9 @@ tb : PROCESS
 	PROCEDURE reset IS
 	BEGIN
 		rst <= '1';
-		WAIT FOR PERIOD * 2;
+		WAIT FOR period * 2;
 		rst <= '0';
-		WAIT FOR PERIOD;
+		WAIT FOR period;
 	END reset;
 	-- Test data procedure
 	PROCEDURE test (CONSTANT TESTDATA : IN std_logic_vector(10 DOWNTO 0)) IS
@@ -92,20 +92,20 @@ BEGIN
 	-- Test data
 	test(PREAMBLE_CODE & "0101");
 	test(PREAMBLE_CODE & "1111");
-	WAIT FOR PERIOD;
+	WAIT FOR period;
 
 	test("0000000" & "0100");
 	test(PREAMBLE_CODE & "0001");
-	WAIT FOR PERIOD;
+	WAIT FOR period;
 
 	bitsample <= '0'; -- disable bitsample 'clock'
 	test("0000000" & "0110");
 	test(PREAMBLE_CODE & "1001");
-	WAIT FOR PERIOD;
+	WAIT FOR period;
 
 	clk_en <= '0'; -- disable clock
 	test(PREAMBLE_CODE & "0101");
 	end_of_sim <= true;
 	WAIT;
 END PROCESS;
-END;
+END;

receiver/receiver.vhd

@@ -0,0 +1,74 @@
+--***************************************
+--* TITLE: Receiver (receiver) 		*
+--* TYPE: Top File			*
+--* AUTHOR: Dylan Van Assche 		*
+--* DATE: 9/12/2017 			*
+--***************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Connect all the layers into 1 VHDL file.
+--2)Principle:
+-- Connect every layer API.
+--3)Inputs:
+-- rx, pn_select, rst, clk, clk_en
+--4)Outputs:
+-- display_b
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+ENTITY receiver IS
+	PORT
+	(
+		clk		: IN std_logic;
+		clk_en		: IN std_logic;
+		rst		: IN std_logic;
+		rx		: IN std_logic;
+		pn_select	: IN std_logic_vector(1 DOWNTO 0);
+		display_b	: OUT std_logic_vector(6 DOWNTO 0)
+	);
+END receiver ;
+ARCHITECTURE behavior OF receiver IS
+	SIGNAL bitsample	: std_logic;
+	SIGNAL databit		: std_logic;
+	SIGNAL preamble		: std_logic_vector(6 DOWNTO 0);
+	SIGNAL data		: std_logic_vector(3 DOWNTO 0); -- received number from transmitter
+BEGIN
+--layers
+application_layer : ENTITY work.application_layer(behavior)
+PORT MAP
+(
+	clk       => clk,
+	clk_en    => clk_en,
+	rst       => rst,
+	bitsample => bitsample,
+	preamble  => preamble,
+	data_in   => data,
+	display_b => display_b
+);
+datalink_layer : ENTITY work.datashiftreg(behavior) -- datalink layer is only 1 component
+PORT MAP
+(
+	clk        => clk,
+	clk_en     => clk_en,
+	rst        => rst,
+	bitsample  => bitsample,
+	databit    => databit,
+	preamble   => preamble,
+	data       => data 
+);
+access_layer : ENTITY work.access_layer(behavior)
+PORT MAP
+(
+	clk		=> clk,
+	clk_en		=> clk_en,
+	rst		=> rst,
+	sdi_spread	=> rx,
+	pn_select	=> pn_select,
+	bitsample_out	=> bitsample,
+	databit		=> databit
+);
+END behavior;

receiver/receiver_test.vhd

@@ -0,0 +1,129 @@
+--***********************************************
+--* TITLE: Receiver TESTBENCH (receiver) 	*
+--* TYPE: Top File				*
+--* AUTHOR: Dylan Van Assche 			*
+--* DATE: 9/12/2017 				*
+--***********************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- TESTBENCH: Connect all the layers into 1 VHDL file.
+--2)Principle:
+-- Connect every layer API.
+--3)Inputs:
+-- rx, pn_select, rst, clk, clk_en
+--4)Outputs:
+-- display_b
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+USE ieee.std_logic_arith.ALL;
+ENTITY receiver_test IS
+END receiver_test;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE structural OF receiver_test IS
+	--initialize signals & constants
+	CONSTANT PERIOD        : TIME := 100 ns;
+	CONSTANT DELAY         : TIME := 10 ns;
+	SIGNAL end_of_sim      : BOOLEAN := false;
+	SIGNAL clk             : std_logic := '0';
+	SIGNAL clk_en          : std_logic := '1';
+	SIGNAL rst             : std_logic := '0';
+	SIGNAL rx	       : std_logic := '0';
+	SIGNAL display_b       : std_logic_vector(6 DOWNTO 0);
+	SIGNAL pn_select       : std_logic_vector(1 DOWNTO 0) := "00";
+	--initialize constants
+	CONSTANT NO_PTRN: std_logic_vector(30 DOWNTO 0) := (OTHERS => '0');
+	CONSTANT PTRN_1 : std_logic_vector(30 DOWNTO 0) := "0100001010111011000111110011010"; -- WARNING: this can change depending on how the transmitter is implemented!
+	CONSTANT PTRN_2 : std_logic_vector(30 DOWNTO 0) := "1110000110101001000101111101100"; -- In case if this isn't working, shift all bit and try again!
+	CONSTANT PTRN_3 : std_logic_vector(30 DOWNTO 0) := "1010001100010010000010001110110";
+BEGIN
+--***********
+--* MAPPING *
+--***********
+uut : ENTITY work.receiver(behavior)
+	PORT MAP
+	(
+		clk		=> clk,
+		clk_en		=> clk_en,
+		rst		=> rst,
+		rx		=> rx,
+		pn_select	=> pn_select,
+		display_b	=> display_b
+	);
+-- Only for synchronous components
+clock : PROCESS
+BEGIN
+	clk <= '0';
+	WAIT FOR PERIOD/2;
+	LOOP
+		clk <= '0';
+		WAIT FOR PERIOD/2;
+		clk <= '1';
+		WAIT FOR PERIOD/2;
+		EXIT WHEN end_of_sim;
+	END LOOP;
+	WAIT;
+END PROCESS clock;
+-- Testbench
+tb : PROCESS
+	-- Reset procedure to initialize the component
+	PROCEDURE reset IS
+	BEGIN
+		rst <= '1';
+		WAIT FOR PERIOD*2;
+		rst <= '0';
+		WAIT FOR PERIOD;
+	END reset;
+	-- Test data procedure
+	PROCEDURE test (CONSTANT TESTPN: IN std_logic_vector(1 DOWNTO 0); CONSTANT TESTDATA: IN std_logic) IS
+	BEGIN
+		pn_select <= TESTPN;
+		rx <= TESTDATA;
+		WAIT FOR PERIOD;
+	END test;
+BEGIN
+	-- Reset at startup
+	reset;
+	-- Test data
+	-- seq_det should be 0 for the next loop:
+	FOR pn_code IN 0 TO 3 LOOP
+	  FOR i IN 0 TO 30 LOOP
+	    test(CONV_STD_LOGIC_VECTOR(pn_code, 2), '1');
+	  END LOOP;
+	END LOOP;
+	-- seq_det should be 1 for the next 3 loops, NO_PTRN isn't used and already visible in the above loop at initialisation:
+	-- pn1
+	FOR i IN 0 TO 30 LOOP
+	    test("01", PTRN_1(30-i));
+	END LOOP;
+	FOR i IN 0 TO 30 LOOP
+	    test("01", PTRN_1(30-i));
+	END LOOP;
+	WAIT FOR PERIOD*3;
+	-- pn2
+	FOR i IN 0 TO 30 LOOP
+	    test("10", PTRN_2(30-i));
+	END LOOP;
+	FOR i IN 0 TO 30 LOOP
+	    test("10", PTRN_2(30-i));
+	END LOOP;
+	WAIT FOR PERIOD*3;
+	-- pn3
+	FOR i IN 0 TO 30 LOOP
+	    test("11", PTRN_3(30-i));
+	END LOOP;FOR i IN 0 TO 30 LOOP
+	    test("11", PTRN_3(30-i));
+	END LOOP;
+	WAIT FOR PERIOD*3;
+
+	end_of_sim <= true;
+	WAIT;
+END PROCESS;
+END;