16bit_shift_adder

Project to Design and Implement a 16-bit Shift Adder (Serial Adder) using Verilog.

This project contains two main .v (verilog) files using which the project runs:

1. adder.v : Main Verilog Code
2. tb_adder.v : Test-bench File

The output in gtkwave format can be viewed from the tb_adder.vcd file.

Note: The program is actually for N-bit Shift Adder. We can change value of 'N' in second line of adder.v and size of input1, input2, answer in tb_adder.v in lines 2-4.