test

#! /usr/bin/vvp
:ivl_version "10.1 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "vhdl_sys";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x7fffbc223550 .scope module, "tb_N_bit_adder" "tb_N_bit_adder" 2 1;
 .timescale 0 0;
v0x7fffbc25fcc0_0 .net "answer", 15 0, L_0x7fffbc269a70;  1 drivers
v0x7fffbc25fd80_0 .var "input1", 15 0;
v0x7fffbc25fe50_0 .var "input2", 15 0;
S_0x7fffbc2381d0 .scope module, "uut" "N_bit_adder" 2 11, 3 1 0, S_0x7fffbc223550;
 .timescale 0 0;
    .port_info 0 /INPUT 16 "input1"
    .port_info 1 /INPUT 16 "input2"
    .port_info 2 /OUTPUT 16 "answer"
P_0x7fffbc217f70 .param/l "N" 0 3 2, +C4<00000000000000000000000000010000>;
v0x7fffbc25f800_0 .net "answer", 15 0, L_0x7fffbc269a70;  alias, 1 drivers
v0x7fffbc25f900_0 .net "carry", 15 0, L_0x7fffbc26a190;  1 drivers
v0x7fffbc25f9e0_0 .net "carry_out", 0 0, L_0x7fffbc26a9d0;  1 drivers
v0x7fffbc25fa80_0 .net "input1", 15 0, v0x7fffbc25fd80_0;  1 drivers
v0x7fffbc25fb60_0 .net "input2", 15 0, v0x7fffbc25fe50_0;  1 drivers
L_0x7fffbc260190 .part v0x7fffbc25fd80_0, 0, 1;
L_0x7fffbc260280 .part v0x7fffbc25fe50_0, 0, 1;
L_0x7fffbc2609a0 .part v0x7fffbc25fd80_0, 1, 1;
L_0x7fffbc260ad0 .part v0x7fffbc25fe50_0, 1, 1;
L_0x7fffbc260c30 .part L_0x7fffbc26a190, 0, 1;
L_0x7fffbc2612d0 .part v0x7fffbc25fd80_0, 2, 1;
L_0x7fffbc2614d0 .part v0x7fffbc25fe50_0, 2, 1;
L_0x7fffbc261690 .part L_0x7fffbc26a190, 1, 1;
L_0x7fffbc261cd0 .part v0x7fffbc25fd80_0, 3, 1;
L_0x7fffbc261e00 .part v0x7fffbc25fe50_0, 3, 1;
L_0x7fffbc261f90 .part L_0x7fffbc26a190, 2, 1;
L_0x7fffbc262580 .part v0x7fffbc25fd80_0, 4, 1;
L_0x7fffbc262720 .part v0x7fffbc25fe50_0, 4, 1;
L_0x7fffbc262850 .part L_0x7fffbc26a190, 3, 1;
L_0x7fffbc262f10 .part v0x7fffbc25fd80_0, 5, 1;
L_0x7fffbc263040 .part v0x7fffbc25fe50_0, 5, 1;
L_0x7fffbc263200 .part L_0x7fffbc26a190, 4, 1;
L_0x7fffbc263870 .part v0x7fffbc25fd80_0, 6, 1;
L_0x7fffbc263a40 .part v0x7fffbc25fe50_0, 6, 1;
L_0x7fffbc263ae0 .part L_0x7fffbc26a190, 5, 1;
L_0x7fffbc2639a0 .part v0x7fffbc25fd80_0, 7, 1;
L_0x7fffbc264170 .part v0x7fffbc25fe50_0, 7, 1;
L_0x7fffbc264360 .part L_0x7fffbc26a190, 6, 1;
L_0x7fffbc2649d0 .part v0x7fffbc25fd80_0, 8, 1;
L_0x7fffbc264bd0 .part v0x7fffbc25fe50_0, 8, 1;
L_0x7fffbc264d00 .part L_0x7fffbc26a190, 7, 1;
L_0x7fffbc265560 .part v0x7fffbc25fd80_0, 9, 1;
L_0x7fffbc265600 .part v0x7fffbc25fe50_0, 9, 1;
L_0x7fffbc265820 .part L_0x7fffbc26a190, 8, 1;
L_0x7fffbc265e90 .part v0x7fffbc25fd80_0, 10, 1;
L_0x7fffbc2660c0 .part v0x7fffbc25fe50_0, 10, 1;
L_0x7fffbc2661f0 .part L_0x7fffbc26a190, 9, 1;
L_0x7fffbc266970 .part v0x7fffbc25fd80_0, 11, 1;
L_0x7fffbc266aa0 .part v0x7fffbc25fe50_0, 11, 1;
L_0x7fffbc266cf0 .part L_0x7fffbc26a190, 10, 1;
L_0x7fffbc267360 .part v0x7fffbc25fd80_0, 12, 1;
L_0x7fffbc266bd0 .part v0x7fffbc25fe50_0, 12, 1;
L_0x7fffbc267650 .part L_0x7fffbc26a190, 11, 1;
L_0x7fffbc267d90 .part v0x7fffbc25fd80_0, 13, 1;
L_0x7fffbc267ec0 .part v0x7fffbc25fe50_0, 13, 1;
L_0x7fffbc268140 .part L_0x7fffbc26a190, 12, 1;
L_0x7fffbc2687b0 .part v0x7fffbc25fd80_0, 14, 1;
L_0x7fffbc268a40 .part v0x7fffbc25fe50_0, 14, 1;
L_0x7fffbc268d80 .part L_0x7fffbc26a190, 13, 1;
L_0x7fffbc269560 .part v0x7fffbc25fd80_0, 15, 1;
L_0x7fffbc269690 .part v0x7fffbc25fe50_0, 15, 1;
L_0x7fffbc269940 .part L_0x7fffbc26a190, 14, 1;
LS_0x7fffbc269a70_0_0 .concat8 [ 1 1 1 1], L_0x7fffbc25ff50, L_0x7fffbc2603e0, L_0x7fffbc260dd0, L_0x7fffbc261880;
LS_0x7fffbc269a70_0_4 .concat8 [ 1 1 1 1], L_0x7fffbc262130, L_0x7fffbc262a90, L_0x7fffbc2633a0, L_0x7fffbc263ca0;
LS_0x7fffbc269a70_0_8 .concat8 [ 1 1 1 1], L_0x7fffbc264500, L_0x7fffbc265090, L_0x7fffbc2659c0, L_0x7fffbc2664a0;
LS_0x7fffbc269a70_0_12 .concat8 [ 1 1 1 1], L_0x7fffbc266e90, L_0x7fffbc2678c0, L_0x7fffbc2682e0, L_0x7fffbc269090;
L_0x7fffbc269a70 .concat8 [ 4 4 4 4], LS_0x7fffbc269a70_0_0, LS_0x7fffbc269a70_0_4, LS_0x7fffbc269a70_0_8, LS_0x7fffbc269a70_0_12;
LS_0x7fffbc26a190_0_0 .concat8 [ 1 1 1 1], L_0x7fffbc260050, L_0x7fffbc260890, L_0x7fffbc2611c0, L_0x7fffbc261bc0;
LS_0x7fffbc26a190_0_4 .concat8 [ 1 1 1 1], L_0x7fffbc262470, L_0x7fffbc262e00, L_0x7fffbc263760, L_0x7fffbc264060;
LS_0x7fffbc26a190_0_8 .concat8 [ 1 1 1 1], L_0x7fffbc2648c0, L_0x7fffbc265450, L_0x7fffbc265d80, L_0x7fffbc266860;
LS_0x7fffbc26a190_0_12 .concat8 [ 1 1 1 1], L_0x7fffbc267250, L_0x7fffbc267c80, L_0x7fffbc2686a0, L_0x7fffbc269450;
L_0x7fffbc26a190 .concat8 [ 4 4 4 4], LS_0x7fffbc26a190_0_0, LS_0x7fffbc26a190_0_4, LS_0x7fffbc26a190_0_8, LS_0x7fffbc26a190_0_12;
L_0x7fffbc26a9d0 .part L_0x7fffbc26a190, 15, 1;
S_0x7fffbc239600 .scope generate, "generate_N_bit_Adder[0]" "generate_N_bit_Adder[0]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc2293c0 .param/l "i" 0 3 9, +C4<00>;
S_0x7fffbc2353b0 .scope generate, "genblk2" "genblk2" 3 11, 3 11 0, S_0x7fffbc239600;
 .timescale 0 0;
S_0x7fffbc2367e0 .scope module, "f" "half_adder" 3 12, 3 20 0, S_0x7fffbc2353b0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /OUTPUT 1 "s"
    .port_info 3 /OUTPUT 1 "c"
L_0x7fffbc25ff50 .functor XOR 1, L_0x7fffbc260190, L_0x7fffbc260280, C4<0>, C4<0>;
L_0x7fffbc260050 .functor AND 1, L_0x7fffbc260190, L_0x7fffbc260280, C4<1>, C4<1>;
v0x7fffbc21da60_0 .net "c", 0 0, L_0x7fffbc260050;  1 drivers
v0x7fffbc21ac40_0 .net "s", 0 0, L_0x7fffbc25ff50;  1 drivers
v0x7fffbc217e20_0 .net "x", 0 0, L_0x7fffbc260190;  1 drivers
v0x7fffbc215000_0 .net "y", 0 0, L_0x7fffbc260280;  1 drivers
S_0x7fffbc2502f0 .scope generate, "generate_N_bit_Adder[1]" "generate_N_bit_Adder[1]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc22c1e0 .param/l "i" 0 3 9, +C4<01>;
S_0x7fffbc250520 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc2502f0;
 .timescale 0 0;
S_0x7fffbc2506a0 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc250520;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc260370 .functor XOR 1, L_0x7fffbc2609a0, L_0x7fffbc260ad0, C4<0>, C4<0>;
L_0x7fffbc2603e0 .functor XOR 1, L_0x7fffbc260370, L_0x7fffbc260c30, C4<0>, C4<0>;
L_0x7fffbc2604a0 .functor AND 1, L_0x7fffbc260ad0, L_0x7fffbc260c30, C4<1>, C4<1>;
L_0x7fffbc2605e0 .functor AND 1, L_0x7fffbc2609a0, L_0x7fffbc260ad0, C4<1>, C4<1>;
L_0x7fffbc2606d0 .functor OR 1, L_0x7fffbc2604a0, L_0x7fffbc2605e0, C4<0>, C4<0>;
L_0x7fffbc2607e0 .functor AND 1, L_0x7fffbc2609a0, L_0x7fffbc260c30, C4<1>, C4<1>;
L_0x7fffbc260890 .functor OR 1, L_0x7fffbc2606d0, L_0x7fffbc2607e0, C4<0>, C4<0>;
v0x7fffbc2121e0_0 .net *"_s0", 0 0, L_0x7fffbc260370;  1 drivers
v0x7fffbc20f380_0 .net *"_s10", 0 0, L_0x7fffbc2607e0;  1 drivers
v0x7fffbc250960_0 .net *"_s4", 0 0, L_0x7fffbc2604a0;  1 drivers
v0x7fffbc250a20_0 .net *"_s6", 0 0, L_0x7fffbc2605e0;  1 drivers
v0x7fffbc250b00_0 .net *"_s8", 0 0, L_0x7fffbc2606d0;  1 drivers
v0x7fffbc250be0_0 .net "c_in", 0 0, L_0x7fffbc260c30;  1 drivers
v0x7fffbc250ca0_0 .net "c_out", 0 0, L_0x7fffbc260890;  1 drivers
v0x7fffbc250d60_0 .net "s", 0 0, L_0x7fffbc2603e0;  1 drivers
v0x7fffbc250e20_0 .net "x", 0 0, L_0x7fffbc2609a0;  1 drivers
v0x7fffbc250ee0_0 .net "y", 0 0, L_0x7fffbc260ad0;  1 drivers
S_0x7fffbc251040 .scope generate, "generate_N_bit_Adder[2]" "generate_N_bit_Adder[2]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc2511e0 .param/l "i" 0 3 9, +C4<010>;
S_0x7fffbc2512a0 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc251040;
 .timescale 0 0;
S_0x7fffbc251470 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc2512a0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc260d60 .functor XOR 1, L_0x7fffbc2612d0, L_0x7fffbc2614d0, C4<0>, C4<0>;
L_0x7fffbc260dd0 .functor XOR 1, L_0x7fffbc260d60, L_0x7fffbc261690, C4<0>, C4<0>;
L_0x7fffbc260e70 .functor AND 1, L_0x7fffbc2614d0, L_0x7fffbc261690, C4<1>, C4<1>;
L_0x7fffbc260f10 .functor AND 1, L_0x7fffbc2612d0, L_0x7fffbc2614d0, C4<1>, C4<1>;
L_0x7fffbc261000 .functor OR 1, L_0x7fffbc260e70, L_0x7fffbc260f10, C4<0>, C4<0>;
L_0x7fffbc261110 .functor AND 1, L_0x7fffbc2612d0, L_0x7fffbc261690, C4<1>, C4<1>;
L_0x7fffbc2611c0 .functor OR 1, L_0x7fffbc261000, L_0x7fffbc261110, C4<0>, C4<0>;
v0x7fffbc251710_0 .net *"_s0", 0 0, L_0x7fffbc260d60;  1 drivers
v0x7fffbc251810_0 .net *"_s10", 0 0, L_0x7fffbc261110;  1 drivers
v0x7fffbc2518f0_0 .net *"_s4", 0 0, L_0x7fffbc260e70;  1 drivers
v0x7fffbc2519e0_0 .net *"_s6", 0 0, L_0x7fffbc260f10;  1 drivers
v0x7fffbc251ac0_0 .net *"_s8", 0 0, L_0x7fffbc261000;  1 drivers
v0x7fffbc251bf0_0 .net "c_in", 0 0, L_0x7fffbc261690;  1 drivers
v0x7fffbc251cb0_0 .net "c_out", 0 0, L_0x7fffbc2611c0;  1 drivers
v0x7fffbc251d70_0 .net "s", 0 0, L_0x7fffbc260dd0;  1 drivers
v0x7fffbc251e30_0 .net "x", 0 0, L_0x7fffbc2612d0;  1 drivers
v0x7fffbc251ef0_0 .net "y", 0 0, L_0x7fffbc2614d0;  1 drivers
S_0x7fffbc252050 .scope generate, "generate_N_bit_Adder[3]" "generate_N_bit_Adder[3]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc2521f0 .param/l "i" 0 3 9, +C4<011>;
S_0x7fffbc2522d0 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc252050;
 .timescale 0 0;
S_0x7fffbc2524a0 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc2522d0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc261810 .functor XOR 1, L_0x7fffbc261cd0, L_0x7fffbc261e00, C4<0>, C4<0>;
L_0x7fffbc261880 .functor XOR 1, L_0x7fffbc261810, L_0x7fffbc261f90, C4<0>, C4<0>;
L_0x7fffbc2618f0 .functor AND 1, L_0x7fffbc261e00, L_0x7fffbc261f90, C4<1>, C4<1>;
L_0x7fffbc261960 .functor AND 1, L_0x7fffbc261cd0, L_0x7fffbc261e00, C4<1>, C4<1>;
L_0x7fffbc261a00 .functor OR 1, L_0x7fffbc2618f0, L_0x7fffbc261960, C4<0>, C4<0>;
L_0x7fffbc261b10 .functor AND 1, L_0x7fffbc261cd0, L_0x7fffbc261f90, C4<1>, C4<1>;
L_0x7fffbc261bc0 .functor OR 1, L_0x7fffbc261a00, L_0x7fffbc261b10, C4<0>, C4<0>;
v0x7fffbc252710_0 .net *"_s0", 0 0, L_0x7fffbc261810;  1 drivers
v0x7fffbc252810_0 .net *"_s10", 0 0, L_0x7fffbc261b10;  1 drivers
v0x7fffbc2528f0_0 .net *"_s4", 0 0, L_0x7fffbc2618f0;  1 drivers
v0x7fffbc2529e0_0 .net *"_s6", 0 0, L_0x7fffbc261960;  1 drivers
v0x7fffbc252ac0_0 .net *"_s8", 0 0, L_0x7fffbc261a00;  1 drivers
v0x7fffbc252bf0_0 .net "c_in", 0 0, L_0x7fffbc261f90;  1 drivers
v0x7fffbc252cb0_0 .net "c_out", 0 0, L_0x7fffbc261bc0;  1 drivers
v0x7fffbc252d70_0 .net "s", 0 0, L_0x7fffbc261880;  1 drivers
v0x7fffbc252e30_0 .net "x", 0 0, L_0x7fffbc261cd0;  1 drivers
v0x7fffbc252f80_0 .net "y", 0 0, L_0x7fffbc261e00;  1 drivers
S_0x7fffbc2530e0 .scope generate, "generate_N_bit_Adder[4]" "generate_N_bit_Adder[4]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc2532d0 .param/l "i" 0 3 9, +C4<0100>;
S_0x7fffbc2533b0 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc2530e0;
 .timescale 0 0;
S_0x7fffbc253580 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc2533b0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc2620c0 .functor XOR 1, L_0x7fffbc262580, L_0x7fffbc262720, C4<0>, C4<0>;
L_0x7fffbc262130 .functor XOR 1, L_0x7fffbc2620c0, L_0x7fffbc262850, C4<0>, C4<0>;
L_0x7fffbc2621a0 .functor AND 1, L_0x7fffbc262720, L_0x7fffbc262850, C4<1>, C4<1>;
L_0x7fffbc262210 .functor AND 1, L_0x7fffbc262580, L_0x7fffbc262720, C4<1>, C4<1>;
L_0x7fffbc2622b0 .functor OR 1, L_0x7fffbc2621a0, L_0x7fffbc262210, C4<0>, C4<0>;
L_0x7fffbc2623c0 .functor AND 1, L_0x7fffbc262580, L_0x7fffbc262850, C4<1>, C4<1>;
L_0x7fffbc262470 .functor OR 1, L_0x7fffbc2622b0, L_0x7fffbc2623c0, C4<0>, C4<0>;
v0x7fffbc2537f0_0 .net *"_s0", 0 0, L_0x7fffbc2620c0;  1 drivers
v0x7fffbc2538f0_0 .net *"_s10", 0 0, L_0x7fffbc2623c0;  1 drivers
v0x7fffbc2539d0_0 .net *"_s4", 0 0, L_0x7fffbc2621a0;  1 drivers
v0x7fffbc253a90_0 .net *"_s6", 0 0, L_0x7fffbc262210;  1 drivers
v0x7fffbc253b70_0 .net *"_s8", 0 0, L_0x7fffbc2622b0;  1 drivers
v0x7fffbc253ca0_0 .net "c_in", 0 0, L_0x7fffbc262850;  1 drivers
v0x7fffbc253d60_0 .net "c_out", 0 0, L_0x7fffbc262470;  1 drivers
v0x7fffbc253e20_0 .net "s", 0 0, L_0x7fffbc262130;  1 drivers
v0x7fffbc253ee0_0 .net "x", 0 0, L_0x7fffbc262580;  1 drivers
v0x7fffbc254030_0 .net "y", 0 0, L_0x7fffbc262720;  1 drivers
S_0x7fffbc254190 .scope generate, "generate_N_bit_Adder[5]" "generate_N_bit_Adder[5]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc254330 .param/l "i" 0 3 9, +C4<0101>;
S_0x7fffbc254410 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc254190;
 .timescale 0 0;
S_0x7fffbc2545e0 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc254410;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc2626b0 .functor XOR 1, L_0x7fffbc262f10, L_0x7fffbc263040, C4<0>, C4<0>;
L_0x7fffbc262a90 .functor XOR 1, L_0x7fffbc2626b0, L_0x7fffbc263200, C4<0>, C4<0>;
L_0x7fffbc262b00 .functor AND 1, L_0x7fffbc263040, L_0x7fffbc263200, C4<1>, C4<1>;
L_0x7fffbc262ba0 .functor AND 1, L_0x7fffbc262f10, L_0x7fffbc263040, C4<1>, C4<1>;
L_0x7fffbc262c40 .functor OR 1, L_0x7fffbc262b00, L_0x7fffbc262ba0, C4<0>, C4<0>;
L_0x7fffbc262d50 .functor AND 1, L_0x7fffbc262f10, L_0x7fffbc263200, C4<1>, C4<1>;
L_0x7fffbc262e00 .functor OR 1, L_0x7fffbc262c40, L_0x7fffbc262d50, C4<0>, C4<0>;
v0x7fffbc254850_0 .net *"_s0", 0 0, L_0x7fffbc2626b0;  1 drivers
v0x7fffbc254950_0 .net *"_s10", 0 0, L_0x7fffbc262d50;  1 drivers
v0x7fffbc254a30_0 .net *"_s4", 0 0, L_0x7fffbc262b00;  1 drivers
v0x7fffbc254b20_0 .net *"_s6", 0 0, L_0x7fffbc262ba0;  1 drivers
v0x7fffbc254c00_0 .net *"_s8", 0 0, L_0x7fffbc262c40;  1 drivers
v0x7fffbc254d30_0 .net "c_in", 0 0, L_0x7fffbc263200;  1 drivers
v0x7fffbc254df0_0 .net "c_out", 0 0, L_0x7fffbc262e00;  1 drivers
v0x7fffbc254eb0_0 .net "s", 0 0, L_0x7fffbc262a90;  1 drivers
v0x7fffbc254f70_0 .net "x", 0 0, L_0x7fffbc262f10;  1 drivers
v0x7fffbc2550c0_0 .net "y", 0 0, L_0x7fffbc263040;  1 drivers
S_0x7fffbc255220 .scope generate, "generate_N_bit_Adder[6]" "generate_N_bit_Adder[6]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc2553c0 .param/l "i" 0 3 9, +C4<0110>;
S_0x7fffbc2554a0 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc255220;
 .timescale 0 0;
S_0x7fffbc255670 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc2554a0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc263330 .functor XOR 1, L_0x7fffbc263870, L_0x7fffbc263a40, C4<0>, C4<0>;
L_0x7fffbc2633a0 .functor XOR 1, L_0x7fffbc263330, L_0x7fffbc263ae0, C4<0>, C4<0>;
L_0x7fffbc263410 .functor AND 1, L_0x7fffbc263a40, L_0x7fffbc263ae0, C4<1>, C4<1>;
L_0x7fffbc2634b0 .functor AND 1, L_0x7fffbc263870, L_0x7fffbc263a40, C4<1>, C4<1>;
L_0x7fffbc2635a0 .functor OR 1, L_0x7fffbc263410, L_0x7fffbc2634b0, C4<0>, C4<0>;
L_0x7fffbc2636b0 .functor AND 1, L_0x7fffbc263870, L_0x7fffbc263ae0, C4<1>, C4<1>;
L_0x7fffbc263760 .functor OR 1, L_0x7fffbc2635a0, L_0x7fffbc2636b0, C4<0>, C4<0>;
v0x7fffbc2558e0_0 .net *"_s0", 0 0, L_0x7fffbc263330;  1 drivers
v0x7fffbc2559e0_0 .net *"_s10", 0 0, L_0x7fffbc2636b0;  1 drivers
v0x7fffbc255ac0_0 .net *"_s4", 0 0, L_0x7fffbc263410;  1 drivers
v0x7fffbc255bb0_0 .net *"_s6", 0 0, L_0x7fffbc2634b0;  1 drivers
v0x7fffbc255c90_0 .net *"_s8", 0 0, L_0x7fffbc2635a0;  1 drivers
v0x7fffbc255dc0_0 .net "c_in", 0 0, L_0x7fffbc263ae0;  1 drivers
v0x7fffbc255e80_0 .net "c_out", 0 0, L_0x7fffbc263760;  1 drivers
v0x7fffbc255f40_0 .net "s", 0 0, L_0x7fffbc2633a0;  1 drivers
v0x7fffbc256000_0 .net "x", 0 0, L_0x7fffbc263870;  1 drivers
v0x7fffbc256150_0 .net "y", 0 0, L_0x7fffbc263a40;  1 drivers
S_0x7fffbc2562b0 .scope generate, "generate_N_bit_Adder[7]" "generate_N_bit_Adder[7]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc256450 .param/l "i" 0 3 9, +C4<0111>;
S_0x7fffbc256530 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc2562b0;
 .timescale 0 0;
S_0x7fffbc256700 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc256530;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc263c30 .functor XOR 1, L_0x7fffbc2639a0, L_0x7fffbc264170, C4<0>, C4<0>;
L_0x7fffbc263ca0 .functor XOR 1, L_0x7fffbc263c30, L_0x7fffbc264360, C4<0>, C4<0>;
L_0x7fffbc263d10 .functor AND 1, L_0x7fffbc264170, L_0x7fffbc264360, C4<1>, C4<1>;
L_0x7fffbc263db0 .functor AND 1, L_0x7fffbc2639a0, L_0x7fffbc264170, C4<1>, C4<1>;
L_0x7fffbc263ea0 .functor OR 1, L_0x7fffbc263d10, L_0x7fffbc263db0, C4<0>, C4<0>;
L_0x7fffbc263fb0 .functor AND 1, L_0x7fffbc2639a0, L_0x7fffbc264360, C4<1>, C4<1>;
L_0x7fffbc264060 .functor OR 1, L_0x7fffbc263ea0, L_0x7fffbc263fb0, C4<0>, C4<0>;
v0x7fffbc256970_0 .net *"_s0", 0 0, L_0x7fffbc263c30;  1 drivers
v0x7fffbc256a70_0 .net *"_s10", 0 0, L_0x7fffbc263fb0;  1 drivers
v0x7fffbc256b50_0 .net *"_s4", 0 0, L_0x7fffbc263d10;  1 drivers
v0x7fffbc256c40_0 .net *"_s6", 0 0, L_0x7fffbc263db0;  1 drivers
v0x7fffbc256d20_0 .net *"_s8", 0 0, L_0x7fffbc263ea0;  1 drivers
v0x7fffbc256e50_0 .net "c_in", 0 0, L_0x7fffbc264360;  1 drivers
v0x7fffbc256f10_0 .net "c_out", 0 0, L_0x7fffbc264060;  1 drivers
v0x7fffbc256fd0_0 .net "s", 0 0, L_0x7fffbc263ca0;  1 drivers
v0x7fffbc257090_0 .net "x", 0 0, L_0x7fffbc2639a0;  1 drivers
v0x7fffbc2571e0_0 .net "y", 0 0, L_0x7fffbc264170;  1 drivers
S_0x7fffbc257340 .scope generate, "generate_N_bit_Adder[8]" "generate_N_bit_Adder[8]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc253280 .param/l "i" 0 3 9, +C4<01000>;
S_0x7fffbc257600 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc257340;
 .timescale 0 0;
S_0x7fffbc2577d0 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc257600;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc264490 .functor XOR 1, L_0x7fffbc2649d0, L_0x7fffbc264bd0, C4<0>, C4<0>;
L_0x7fffbc264500 .functor XOR 1, L_0x7fffbc264490, L_0x7fffbc264d00, C4<0>, C4<0>;
L_0x7fffbc264570 .functor AND 1, L_0x7fffbc264bd0, L_0x7fffbc264d00, C4<1>, C4<1>;
L_0x7fffbc264610 .functor AND 1, L_0x7fffbc2649d0, L_0x7fffbc264bd0, C4<1>, C4<1>;
L_0x7fffbc264700 .functor OR 1, L_0x7fffbc264570, L_0x7fffbc264610, C4<0>, C4<0>;
L_0x7fffbc264810 .functor AND 1, L_0x7fffbc2649d0, L_0x7fffbc264d00, C4<1>, C4<1>;
L_0x7fffbc2648c0 .functor OR 1, L_0x7fffbc264700, L_0x7fffbc264810, C4<0>, C4<0>;
v0x7fffbc257a40_0 .net *"_s0", 0 0, L_0x7fffbc264490;  1 drivers
v0x7fffbc257b40_0 .net *"_s10", 0 0, L_0x7fffbc264810;  1 drivers
v0x7fffbc257c20_0 .net *"_s4", 0 0, L_0x7fffbc264570;  1 drivers
v0x7fffbc257d10_0 .net *"_s6", 0 0, L_0x7fffbc264610;  1 drivers
v0x7fffbc257df0_0 .net *"_s8", 0 0, L_0x7fffbc264700;  1 drivers
v0x7fffbc257f20_0 .net "c_in", 0 0, L_0x7fffbc264d00;  1 drivers
v0x7fffbc257fe0_0 .net "c_out", 0 0, L_0x7fffbc2648c0;  1 drivers
v0x7fffbc2580a0_0 .net "s", 0 0, L_0x7fffbc264500;  1 drivers
v0x7fffbc258160_0 .net "x", 0 0, L_0x7fffbc2649d0;  1 drivers
v0x7fffbc2582b0_0 .net "y", 0 0, L_0x7fffbc264bd0;  1 drivers
S_0x7fffbc258410 .scope generate, "generate_N_bit_Adder[9]" "generate_N_bit_Adder[9]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc2585b0 .param/l "i" 0 3 9, +C4<01001>;
S_0x7fffbc258690 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc258410;
 .timescale 0 0;
S_0x7fffbc258860 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc258690;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc265020 .functor XOR 1, L_0x7fffbc265560, L_0x7fffbc265600, C4<0>, C4<0>;
L_0x7fffbc265090 .functor XOR 1, L_0x7fffbc265020, L_0x7fffbc265820, C4<0>, C4<0>;
L_0x7fffbc265100 .functor AND 1, L_0x7fffbc265600, L_0x7fffbc265820, C4<1>, C4<1>;
L_0x7fffbc2651a0 .functor AND 1, L_0x7fffbc265560, L_0x7fffbc265600, C4<1>, C4<1>;
L_0x7fffbc265290 .functor OR 1, L_0x7fffbc265100, L_0x7fffbc2651a0, C4<0>, C4<0>;
L_0x7fffbc2653a0 .functor AND 1, L_0x7fffbc265560, L_0x7fffbc265820, C4<1>, C4<1>;
L_0x7fffbc265450 .functor OR 1, L_0x7fffbc265290, L_0x7fffbc2653a0, C4<0>, C4<0>;
v0x7fffbc258ad0_0 .net *"_s0", 0 0, L_0x7fffbc265020;  1 drivers
v0x7fffbc258bd0_0 .net *"_s10", 0 0, L_0x7fffbc2653a0;  1 drivers
v0x7fffbc258cb0_0 .net *"_s4", 0 0, L_0x7fffbc265100;  1 drivers
v0x7fffbc258da0_0 .net *"_s6", 0 0, L_0x7fffbc2651a0;  1 drivers
v0x7fffbc258e80_0 .net *"_s8", 0 0, L_0x7fffbc265290;  1 drivers
v0x7fffbc258fb0_0 .net "c_in", 0 0, L_0x7fffbc265820;  1 drivers
v0x7fffbc259070_0 .net "c_out", 0 0, L_0x7fffbc265450;  1 drivers
v0x7fffbc259130_0 .net "s", 0 0, L_0x7fffbc265090;  1 drivers
v0x7fffbc2591f0_0 .net "x", 0 0, L_0x7fffbc265560;  1 drivers
v0x7fffbc259340_0 .net "y", 0 0, L_0x7fffbc265600;  1 drivers
S_0x7fffbc2594a0 .scope generate, "generate_N_bit_Adder[10]" "generate_N_bit_Adder[10]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc259640 .param/l "i" 0 3 9, +C4<01010>;
S_0x7fffbc259720 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc2594a0;
 .timescale 0 0;
S_0x7fffbc2598f0 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc259720;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc265950 .functor XOR 1, L_0x7fffbc265e90, L_0x7fffbc2660c0, C4<0>, C4<0>;
L_0x7fffbc2659c0 .functor XOR 1, L_0x7fffbc265950, L_0x7fffbc2661f0, C4<0>, C4<0>;
L_0x7fffbc265a30 .functor AND 1, L_0x7fffbc2660c0, L_0x7fffbc2661f0, C4<1>, C4<1>;
L_0x7fffbc265ad0 .functor AND 1, L_0x7fffbc265e90, L_0x7fffbc2660c0, C4<1>, C4<1>;
L_0x7fffbc265bc0 .functor OR 1, L_0x7fffbc265a30, L_0x7fffbc265ad0, C4<0>, C4<0>;
L_0x7fffbc265cd0 .functor AND 1, L_0x7fffbc265e90, L_0x7fffbc2661f0, C4<1>, C4<1>;
L_0x7fffbc265d80 .functor OR 1, L_0x7fffbc265bc0, L_0x7fffbc265cd0, C4<0>, C4<0>;
v0x7fffbc259b60_0 .net *"_s0", 0 0, L_0x7fffbc265950;  1 drivers
v0x7fffbc259c60_0 .net *"_s10", 0 0, L_0x7fffbc265cd0;  1 drivers
v0x7fffbc259d40_0 .net *"_s4", 0 0, L_0x7fffbc265a30;  1 drivers
v0x7fffbc259e30_0 .net *"_s6", 0 0, L_0x7fffbc265ad0;  1 drivers
v0x7fffbc259f10_0 .net *"_s8", 0 0, L_0x7fffbc265bc0;  1 drivers
v0x7fffbc25a040_0 .net "c_in", 0 0, L_0x7fffbc2661f0;  1 drivers
v0x7fffbc25a100_0 .net "c_out", 0 0, L_0x7fffbc265d80;  1 drivers
v0x7fffbc25a1c0_0 .net "s", 0 0, L_0x7fffbc2659c0;  1 drivers
v0x7fffbc25a280_0 .net "x", 0 0, L_0x7fffbc265e90;  1 drivers
v0x7fffbc25a3d0_0 .net "y", 0 0, L_0x7fffbc2660c0;  1 drivers
S_0x7fffbc25a530 .scope generate, "generate_N_bit_Adder[11]" "generate_N_bit_Adder[11]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc25a6d0 .param/l "i" 0 3 9, +C4<01011>;
S_0x7fffbc25a7b0 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc25a530;
 .timescale 0 0;
S_0x7fffbc25a980 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc25a7b0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc266430 .functor XOR 1, L_0x7fffbc266970, L_0x7fffbc266aa0, C4<0>, C4<0>;
L_0x7fffbc2664a0 .functor XOR 1, L_0x7fffbc266430, L_0x7fffbc266cf0, C4<0>, C4<0>;
L_0x7fffbc266510 .functor AND 1, L_0x7fffbc266aa0, L_0x7fffbc266cf0, C4<1>, C4<1>;
L_0x7fffbc2665b0 .functor AND 1, L_0x7fffbc266970, L_0x7fffbc266aa0, C4<1>, C4<1>;
L_0x7fffbc2666a0 .functor OR 1, L_0x7fffbc266510, L_0x7fffbc2665b0, C4<0>, C4<0>;
L_0x7fffbc2667b0 .functor AND 1, L_0x7fffbc266970, L_0x7fffbc266cf0, C4<1>, C4<1>;
L_0x7fffbc266860 .functor OR 1, L_0x7fffbc2666a0, L_0x7fffbc2667b0, C4<0>, C4<0>;
v0x7fffbc25abf0_0 .net *"_s0", 0 0, L_0x7fffbc266430;  1 drivers
v0x7fffbc25acf0_0 .net *"_s10", 0 0, L_0x7fffbc2667b0;  1 drivers
v0x7fffbc25add0_0 .net *"_s4", 0 0, L_0x7fffbc266510;  1 drivers
v0x7fffbc25aec0_0 .net *"_s6", 0 0, L_0x7fffbc2665b0;  1 drivers
v0x7fffbc25afa0_0 .net *"_s8", 0 0, L_0x7fffbc2666a0;  1 drivers
v0x7fffbc25b0d0_0 .net "c_in", 0 0, L_0x7fffbc266cf0;  1 drivers
v0x7fffbc25b190_0 .net "c_out", 0 0, L_0x7fffbc266860;  1 drivers
v0x7fffbc25b250_0 .net "s", 0 0, L_0x7fffbc2664a0;  1 drivers
v0x7fffbc25b310_0 .net "x", 0 0, L_0x7fffbc266970;  1 drivers
v0x7fffbc25b460_0 .net "y", 0 0, L_0x7fffbc266aa0;  1 drivers
S_0x7fffbc25b5c0 .scope generate, "generate_N_bit_Adder[12]" "generate_N_bit_Adder[12]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc25b760 .param/l "i" 0 3 9, +C4<01100>;
S_0x7fffbc25b840 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc25b5c0;
 .timescale 0 0;
S_0x7fffbc25ba10 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc25b840;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc266e20 .functor XOR 1, L_0x7fffbc267360, L_0x7fffbc266bd0, C4<0>, C4<0>;
L_0x7fffbc266e90 .functor XOR 1, L_0x7fffbc266e20, L_0x7fffbc267650, C4<0>, C4<0>;
L_0x7fffbc266f00 .functor AND 1, L_0x7fffbc266bd0, L_0x7fffbc267650, C4<1>, C4<1>;
L_0x7fffbc266fa0 .functor AND 1, L_0x7fffbc267360, L_0x7fffbc266bd0, C4<1>, C4<1>;
L_0x7fffbc267090 .functor OR 1, L_0x7fffbc266f00, L_0x7fffbc266fa0, C4<0>, C4<0>;
L_0x7fffbc2671a0 .functor AND 1, L_0x7fffbc267360, L_0x7fffbc267650, C4<1>, C4<1>;
L_0x7fffbc267250 .functor OR 1, L_0x7fffbc267090, L_0x7fffbc2671a0, C4<0>, C4<0>;
v0x7fffbc25bc80_0 .net *"_s0", 0 0, L_0x7fffbc266e20;  1 drivers
v0x7fffbc25bd80_0 .net *"_s10", 0 0, L_0x7fffbc2671a0;  1 drivers
v0x7fffbc25be60_0 .net *"_s4", 0 0, L_0x7fffbc266f00;  1 drivers
v0x7fffbc25bf50_0 .net *"_s6", 0 0, L_0x7fffbc266fa0;  1 drivers
v0x7fffbc25c030_0 .net *"_s8", 0 0, L_0x7fffbc267090;  1 drivers
v0x7fffbc25c160_0 .net "c_in", 0 0, L_0x7fffbc267650;  1 drivers
v0x7fffbc25c220_0 .net "c_out", 0 0, L_0x7fffbc267250;  1 drivers
v0x7fffbc25c2e0_0 .net "s", 0 0, L_0x7fffbc266e90;  1 drivers
v0x7fffbc25c3a0_0 .net "x", 0 0, L_0x7fffbc267360;  1 drivers
v0x7fffbc25c4f0_0 .net "y", 0 0, L_0x7fffbc266bd0;  1 drivers
S_0x7fffbc25c650 .scope generate, "generate_N_bit_Adder[13]" "generate_N_bit_Adder[13]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc25c7f0 .param/l "i" 0 3 9, +C4<01101>;
S_0x7fffbc25c8d0 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc25c650;
 .timescale 0 0;
S_0x7fffbc25caa0 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc25c8d0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc266c70 .functor XOR 1, L_0x7fffbc267d90, L_0x7fffbc267ec0, C4<0>, C4<0>;
L_0x7fffbc2678c0 .functor XOR 1, L_0x7fffbc266c70, L_0x7fffbc268140, C4<0>, C4<0>;
L_0x7fffbc267930 .functor AND 1, L_0x7fffbc267ec0, L_0x7fffbc268140, C4<1>, C4<1>;
L_0x7fffbc2679d0 .functor AND 1, L_0x7fffbc267d90, L_0x7fffbc267ec0, C4<1>, C4<1>;
L_0x7fffbc267ac0 .functor OR 1, L_0x7fffbc267930, L_0x7fffbc2679d0, C4<0>, C4<0>;
L_0x7fffbc267bd0 .functor AND 1, L_0x7fffbc267d90, L_0x7fffbc268140, C4<1>, C4<1>;
L_0x7fffbc267c80 .functor OR 1, L_0x7fffbc267ac0, L_0x7fffbc267bd0, C4<0>, C4<0>;
v0x7fffbc25cd10_0 .net *"_s0", 0 0, L_0x7fffbc266c70;  1 drivers
v0x7fffbc25ce10_0 .net *"_s10", 0 0, L_0x7fffbc267bd0;  1 drivers
v0x7fffbc25cef0_0 .net *"_s4", 0 0, L_0x7fffbc267930;  1 drivers
v0x7fffbc25cfe0_0 .net *"_s6", 0 0, L_0x7fffbc2679d0;  1 drivers
v0x7fffbc25d0c0_0 .net *"_s8", 0 0, L_0x7fffbc267ac0;  1 drivers
v0x7fffbc25d1f0_0 .net "c_in", 0 0, L_0x7fffbc268140;  1 drivers
v0x7fffbc25d2b0_0 .net "c_out", 0 0, L_0x7fffbc267c80;  1 drivers
v0x7fffbc25d370_0 .net "s", 0 0, L_0x7fffbc2678c0;  1 drivers
v0x7fffbc25d430_0 .net "x", 0 0, L_0x7fffbc267d90;  1 drivers
v0x7fffbc25d580_0 .net "y", 0 0, L_0x7fffbc267ec0;  1 drivers
S_0x7fffbc25d6e0 .scope generate, "generate_N_bit_Adder[14]" "generate_N_bit_Adder[14]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc25d880 .param/l "i" 0 3 9, +C4<01110>;
S_0x7fffbc25d960 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc25d6e0;
 .timescale 0 0;
S_0x7fffbc25db30 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc25d960;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc268270 .functor XOR 1, L_0x7fffbc2687b0, L_0x7fffbc268a40, C4<0>, C4<0>;
L_0x7fffbc2682e0 .functor XOR 1, L_0x7fffbc268270, L_0x7fffbc268d80, C4<0>, C4<0>;
L_0x7fffbc268350 .functor AND 1, L_0x7fffbc268a40, L_0x7fffbc268d80, C4<1>, C4<1>;
L_0x7fffbc2683f0 .functor AND 1, L_0x7fffbc2687b0, L_0x7fffbc268a40, C4<1>, C4<1>;
L_0x7fffbc2684e0 .functor OR 1, L_0x7fffbc268350, L_0x7fffbc2683f0, C4<0>, C4<0>;
L_0x7fffbc2685f0 .functor AND 1, L_0x7fffbc2687b0, L_0x7fffbc268d80, C4<1>, C4<1>;
L_0x7fffbc2686a0 .functor OR 1, L_0x7fffbc2684e0, L_0x7fffbc2685f0, C4<0>, C4<0>;
v0x7fffbc25dda0_0 .net *"_s0", 0 0, L_0x7fffbc268270;  1 drivers
v0x7fffbc25dea0_0 .net *"_s10", 0 0, L_0x7fffbc2685f0;  1 drivers
v0x7fffbc25df80_0 .net *"_s4", 0 0, L_0x7fffbc268350;  1 drivers
v0x7fffbc25e070_0 .net *"_s6", 0 0, L_0x7fffbc2683f0;  1 drivers
v0x7fffbc25e150_0 .net *"_s8", 0 0, L_0x7fffbc2684e0;  1 drivers
v0x7fffbc25e280_0 .net "c_in", 0 0, L_0x7fffbc268d80;  1 drivers
v0x7fffbc25e340_0 .net "c_out", 0 0, L_0x7fffbc2686a0;  1 drivers
v0x7fffbc25e400_0 .net "s", 0 0, L_0x7fffbc2682e0;  1 drivers
v0x7fffbc25e4c0_0 .net "x", 0 0, L_0x7fffbc2687b0;  1 drivers
v0x7fffbc25e610_0 .net "y", 0 0, L_0x7fffbc268a40;  1 drivers
S_0x7fffbc25e770 .scope generate, "generate_N_bit_Adder[15]" "generate_N_bit_Adder[15]" 3 9, 3 9 0, S_0x7fffbc2381d0;
 .timescale 0 0;
P_0x7fffbc25e910 .param/l "i" 0 3 9, +C4<01111>;
S_0x7fffbc25e9f0 .scope generate, "genblk3" "genblk3" 3 11, 3 11 0, S_0x7fffbc25e770;
 .timescale 0 0;
S_0x7fffbc25ebc0 .scope module, "f" "full_adder" 3 14, 3 27 0, S_0x7fffbc25e9f0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "x"
    .port_info 1 /INPUT 1 "y"
    .port_info 2 /INPUT 1 "c_in"
    .port_info 3 /OUTPUT 1 "s"
    .port_info 4 /OUTPUT 1 "c_out"
L_0x7fffbc269020 .functor XOR 1, L_0x7fffbc269560, L_0x7fffbc269690, C4<0>, C4<0>;
L_0x7fffbc269090 .functor XOR 1, L_0x7fffbc269020, L_0x7fffbc269940, C4<0>, C4<0>;
L_0x7fffbc269100 .functor AND 1, L_0x7fffbc269690, L_0x7fffbc269940, C4<1>, C4<1>;
L_0x7fffbc2691a0 .functor AND 1, L_0x7fffbc269560, L_0x7fffbc269690, C4<1>, C4<1>;
L_0x7fffbc269290 .functor OR 1, L_0x7fffbc269100, L_0x7fffbc2691a0, C4<0>, C4<0>;
L_0x7fffbc2693a0 .functor AND 1, L_0x7fffbc269560, L_0x7fffbc269940, C4<1>, C4<1>;
L_0x7fffbc269450 .functor OR 1, L_0x7fffbc269290, L_0x7fffbc2693a0, C4<0>, C4<0>;
v0x7fffbc25ee30_0 .net *"_s0", 0 0, L_0x7fffbc269020;  1 drivers
v0x7fffbc25ef30_0 .net *"_s10", 0 0, L_0x7fffbc2693a0;  1 drivers
v0x7fffbc25f010_0 .net *"_s4", 0 0, L_0x7fffbc269100;  1 drivers
v0x7fffbc25f100_0 .net *"_s6", 0 0, L_0x7fffbc2691a0;  1 drivers
v0x7fffbc25f1e0_0 .net *"_s8", 0 0, L_0x7fffbc269290;  1 drivers
v0x7fffbc25f310_0 .net "c_in", 0 0, L_0x7fffbc269940;  1 drivers
v0x7fffbc25f3d0_0 .net "c_out", 0 0, L_0x7fffbc269450;  1 drivers
v0x7fffbc25f490_0 .net "s", 0 0, L_0x7fffbc269090;  1 drivers
v0x7fffbc25f550_0 .net "x", 0 0, L_0x7fffbc269560;  1 drivers
v0x7fffbc25f6a0_0 .net "y", 0 0, L_0x7fffbc269690;  1 drivers
    .scope S_0x7fffbc223550;
T_0 ;
    %vpi_call 2 7 "$dumpfile", "tb_adder.vcd" {0 0 0};
    %vpi_call 2 8 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x7fffbc223550 {0 0 0};
    %end;
    .thread T_0;
    .scope S_0x7fffbc223550;
T_1 ;
    %pushi/vec4 1209, 0, 16;
    %store/vec4 v0x7fffbc25fd80_0, 0, 16;
    %pushi/vec4 1000, 0, 16;
    %store/vec4 v0x7fffbc25fe50_0, 0, 16;
    %delay 100, 0;
    %end;
    .thread T_1;
    .scope S_0x7fffbc223550;
T_2 ;
    %vpi_call 2 25 "$monitor", "Input1=%d, Input2=%d, Output=%d", v0x7fffbc25fd80_0, v0x7fffbc25fe50_0, v0x7fffbc25fcc0_0 {0 0 0};
    %end;
    .thread T_2;
# The file index is used to find the file name in the following table.
:file_names 4;
    "N/A";
    "<interactive>";
    "tb_adder.v";
    "adder.v";