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drop attributes attached to nested generate regions
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zachjs committed Oct 27, 2024
1 parent 24ab7ae commit 7808819
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Showing 3 changed files with 13 additions and 1 deletion.
2 changes: 2 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,8 @@
declarations after inlining
* Fixed inlining of interfaces and interface-bound modules containing port
declarations tagged with an attribute
* Fixed stray attributes producing invalid nested output when attached to
inlined interfaces and interface-bounds modules
* Fixed `` `resetall `` not resetting the `` `default_nettype ``

### Other Enhancements
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10 changes: 9 additions & 1 deletion src/Convert/Traverse.hs
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Expand Up @@ -139,6 +139,8 @@ collectDescriptionsM = mapM_
breakGenerate :: ModuleItem -> [ModuleItem] -> [ModuleItem]
breakGenerate (Generate genItems) items =
foldr breakGenerateStep items genItems
breakGenerate (MIAttr _ (Generate genItems)) items =
foldr breakGenerateStep items genItems
breakGenerate item items = item : items

breakGenerateStep :: GenItem -> [ModuleItem] -> [ModuleItem]
Expand Down Expand Up @@ -1064,8 +1066,14 @@ traverseNestedGenItemsM mapper = fullMapper
traverseNestedGenItems :: Mapper GenItem -> Mapper GenItem
traverseNestedGenItems = unmonad traverseNestedGenItemsM

innerGenItems :: ModuleItem -> Maybe [GenItem]
innerGenItems (MIAttr _ item) = innerGenItems item
innerGenItems (Generate items) = Just items
innerGenItems _ = Nothing

flattenGenBlocks :: GenItem -> [GenItem]
flattenGenBlocks (GenModuleItem (Generate items)) = items
flattenGenBlocks (GenModuleItem item)
| Just items <- innerGenItems item = items
flattenGenBlocks (GenFor _ _ _ GenNull) = []
flattenGenBlocks GenNull = []
flattenGenBlocks other = [other]
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2 changes: 2 additions & 0 deletions test/core/interface_array.sv
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Expand Up @@ -76,6 +76,7 @@ module ModuleB(is);
bn.tick;
endtask
initial $display("Hello I'm ModuleB %0d!", WIDTH);
(* this_attribute_is_ignored *)
ModuleBNested #(WIDTH) bn(is);
endmodule

Expand All @@ -96,6 +97,7 @@ endmodule
module top;
logic inp;

(* this_attribute_is_ignored *)
Interface intfX[2:0](inp);

ModuleA #(0) xa2(intfX[2]);
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