[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (llvm…

…#112548)
transmuter-lp · Nov 6, 2024 · 38fffa6 · 38fffa6
1 parent 5a06219
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diff --git a/clang/test/CodeGen/PowerPC/altivec.c b/clang/test/CodeGen/PowerPC/altivec.c
@@ -12,8 +12,8 @@
 // RUN: %clang -S -emit-llvm -maltivec -mabi=vec-default -mcpu=pwr8 --target=powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // Check initialization
 
-vector int test0 = (vector int)(1);       // CHECK: @test0 ={{.*}} global <4 x i32> <i32 1, i32 1, i32 1, i32 1>
-vector float test1 = (vector float)(1.0); // CHECK: @test1 ={{.*}} global <4 x float> <float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}>
+vector int test0 = (vector int)(1);       // CHECK: @test0 ={{.*}} global <4 x i32> splat (i32 1)
+vector float test1 = (vector float)(1.0); // CHECK: @test1 ={{.*}} global <4 x float> splat (float 1.000000e+{{0+}})
 
 // CHECK-BE: @v1 ={{.*}} global <16 x i8> <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 2, i8 0, i8 0, i8 0, i8 3, i8 0, i8 0, i8 0, i8 4>
 // CHECK-LE: @v1 ={{.*}} global <16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 2, i8 0, i8 0, i8 0, i8 3, i8 0, i8 0, i8 0, i8 4, i8 0, i8 0, i8 0>
@@ -32,8 +32,8 @@ void test2(void)
 {
   vector int vi;
   vector float vf;
-  vi = (vector int)(1);             // CHECK: <i32 1, i32 1, i32 1, i32 1>
-  vf = (vector float)(1.0);         // CHECK: <float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}>
+  vi = (vector int)(1);             // CHECK: splat (i32 1)
+  vf = (vector float)(1.0);         // CHECK: splat (float 1.000000e+{{0+}})
   vi = (vector int)(1, 2, 3, 4);    // CHECK: <i32 1, i32 2, i32 3, i32 4>
   vi = (vector int)(1, 2, 3, 4, 5); // CHECK: <i32 1, i32 2, i32 3, i32 4>
 
@@ -46,9 +46,9 @@ void test2(void)
 // Check pre/post increment/decrement
 void test3(void) {
   vector int vi;
-  vi++;                                    // CHECK: add <4 x i32> {{.*}} <i32 1, i32 1, i32 1, i32 1>
+  vi++;                                    // CHECK: add <4 x i32> {{.*}} splat (i32 1)
   vector unsigned int vui;
-  --vui;                                   // CHECK: add <4 x i32> {{.*}} <i32 -1, i32 -1, i32 -1, i32 -1>
+  --vui;                                   // CHECK: add <4 x i32> {{.*}} splat (i32 -1)
   vector float vf;
-  vf++;                                    // CHECK: fadd <4 x float> {{.*}} <float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}, float 1.000000e+{{0+}}>
+  vf++;                                    // CHECK: fadd <4 x float> {{.*}} splat (float 1.000000e+{{0+}})
 }
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c b/clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c b/clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
@@ -42,7 +42,7 @@ vector double test_flags_recipdivd() {
 // CHECK-LABEL: @test_flags_rsqrtf(
 // CHECK:    [[TMP0:%.*]] = load <4 x float>, ptr @a, align 16
 // CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP0]])
-// CHECK-NEXT:    [[RSQRT:%.*]] = fdiv fast <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, [[TMP1]]
+// CHECK-NEXT:    [[RSQRT:%.*]] = fdiv fast <4 x float> splat (float 1.000000e+00), [[TMP1]]
 // CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, ptr @b, align 16
 // CHECK-NEXT:    [[ADD:%.*]] = fadd <4 x float> [[RSQRT]], [[TMP2]]
 // CHECK-NEXT:    ret <4 x float> [[ADD]]
@@ -54,7 +54,7 @@ vector float test_flags_rsqrtf() {
 // CHECK-LABEL: @test_flags_rsqrtd(
 // CHECK:    [[TMP0:%.*]] = load <2 x double>, ptr @d, align 16
 // CHECK-NEXT:    [[TMP1:%.*]] = call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> [[TMP0]])
-// CHECK-NEXT:    [[RSQRT:%.*]] = fdiv fast <2 x double> <double 1.000000e+00, double 1.000000e+00>, [[TMP1]]
+// CHECK-NEXT:    [[RSQRT:%.*]] = fdiv fast <2 x double> splat (double 1.000000e+00), [[TMP1]]
 // CHECK-NEXT:    [[TMP2:%.*]] = load <2 x double>, ptr @e, align 16
 // CHECK-NEXT:    [[ADD:%.*]] = fadd <2 x double> [[RSQRT]], [[TMP2]]
 // CHECK-NEXT:    ret <2 x double> [[ADD]]

diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
@@ -1535,17 +1535,17 @@ vector unsigned long long test_vec_extracth_ul(void) {
 }
 
 vector signed int test_vec_vec_splati_si(void) {
-  // CHECK: ret <4 x i32> <i32 -17, i32 -17, i32 -17, i32 -17>
+  // CHECK: ret <4 x i32> splat (i32 -17)
   return vec_splati(-17);
 }
 
 vector unsigned int test_vec_vec_splati_ui(void) {
-  // CHECK: ret <4 x i32> <i32 16, i32 16, i32 16, i32 16>
+  // CHECK: ret <4 x i32> splat (i32 16)
   return vec_splati(16U);
 }
 
 vector float test_vec_vec_splati_f(void) {
-  // CHECK: ret <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
+  // CHECK: ret <4 x float> splat (float 1.000000e+00)
   return vec_splati(1.0f);
 }
 
@@ -1863,23 +1863,23 @@ vector bool __int128 test_vec_cmpeq_bool_int128(void) {
 vector bool __int128 test_vec_cmpne_s128(void) {
   // CHECK-LABEL: @test_vec_cmpne_s128(
   // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
-  // CHECK-NEXT: %not.i = xor <1 x i128> %4, <i128 -1>
+  // CHECK-NEXT: %not.i = xor <1 x i128> %4, splat (i128 -1)
   // CHECK-NEXT: ret <1 x i128> %not.i
   return vec_cmpne(vsi128a, vsi128b);
 }
 
 vector bool __int128 test_vec_cmpne_u128(void) {
   // CHECK-LABEL: @test_vec_cmpne_u128(
   // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
-  // CHECK-NEXT: xor <1 x i128> %4, <i128 -1>
+  // CHECK-NEXT: xor <1 x i128> %4, splat (i128 -1)
   // CHECK-NEXT: ret <1 x i128>
   return vec_cmpne(vui128a, vui128b);
 }
 
 vector bool __int128 test_vec_cmpne_bool_int128(void) {
   // CHECK-LABEL: @test_vec_cmpne_bool_int128(
   // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
-  // CHECK-NEXT: xor <1 x i128> %4, <i128 -1>
+  // CHECK-NEXT: xor <1 x i128> %4, splat (i128 -1)
   // CHECK-NEXT: ret <1 x i128>
   return vec_cmpne(vbi128a, vbi128b);
 }
@@ -1915,31 +1915,31 @@ vector bool __int128 test_vec_cmplt_u128(void) {
 vector bool __int128 test_vec_cmpge_s128(void) {
   // CHECK-LABEL: @test_vec_cmpge_s128(
   // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128>
-  // CHECK-NEXT: xor <1 x i128> %6, <i128 -1>
+  // CHECK-NEXT: xor <1 x i128> %6, splat (i128 -1)
   // CHECK-NEXT: ret <1 x i128>
   return vec_cmpge(vsi128a, vsi128b);
 }
 
 vector bool __int128 test_vec_cmpge_u128(void) {
   // CHECK-LABEL: @test_vec_cmpge_u128(
   // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128>
-  // CHECK-NEXT: xor <1 x i128> %6, <i128 -1>
+  // CHECK-NEXT: xor <1 x i128> %6, splat (i128 -1)
   // CHECK-NEXT: ret <1 x i128>
   return vec_cmpge(vui128a, vui128b);
 }
 
 vector bool __int128 test_vec_cmple_s128(void) {
   // CHECK-LABEL: @test_vec_cmple_s128(
   // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128>
-  // CHECK-NEXT: xor <1 x i128> %8, <i128 -1>
+  // CHECK-NEXT: xor <1 x i128> %8, splat (i128 -1)
   // CHECK-NEXT: ret <1 x i128>
   return vec_cmple(vsi128a, vsi128b);
 }
 
 vector bool __int128 test_vec_cmple_u128(void) {
   // CHECK-LABEL: @test_vec_cmple_u128(
   // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128>
-  // CHECK-NEXT: xor <1 x i128> %8, <i128 -1>
+  // CHECK-NEXT: xor <1 x i128> %8, splat (i128 -1)
   // CHECK-NEXT: ret <1 x i128>
   return vec_cmple(vui128a, vui128b);
 }