DDR3 Controller, 16 read, 16 write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included. [This fork is only a mirror, not for development]

BBC micro - Demistified for Deca & Neptuno. [This fork is only a mirror, not for development]

Gateware for the Terasic/Arrow DECA board, to become a USB2 high speed audio interface. [This fork is only a mirror, not for development]

Atari ST/STe core demistyfied. See Readme in board folder (Deca, ...)

Repo that shows how to use the VexRiscv with OpenOCD and semihosting.

VexRiscv cpu on FPGA. [This fork is only a mirror, not for development]

Template with latest framework for SoCkit (MiSTer)

Dual 32 MB SDRAM + 2 MB SRAM MiSTer module with 3 extra pins for DECA retro cape 2

The Terasic DECA board as a mandelbrot accelerator. [This fork is only a mirror, not for development]

Sega Master System Sockit (MiSTer)

PSX for SoCkit (MiSTer firmware)

Sharp X68000 for MiSTer

NES for SoCkit (MiSTer firmware)

NeoGeo for Sockit (MiSTer)

Arcade: Bomb Jack for Terasic/Arrow SoCkit

Retro cape (addon) for DECA FPGA

Oric-1 and Oric Atmos for Sockit (MiSTer)

Commodore C16 and Plus/4 for Sockit (MiSTer)

Flappy Bird core for MiSTer, MiST, DeMiSTify, Xilinx, GoWin, ...

Cave 68K arcade classics for Sockit (Mister)