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gate-level-simulation

Here are 9 public repositories matching this topic...

embedded-explorer / Open-Source-RTL-Design

This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop

vsd yosys gate-level-simulation open-source-rtl

Updated Jun 6, 2021
Verilog

RohanNagar / parallel-logic-networks

Gate-Level Simulation on a GPU

gpu parallel-computing vivado logic-gates gate-level-simulation

Updated Nov 22, 2016
C++

ChunChih3310 / Ultra-Synthesis-Automation-and-Gate-Level-Integration

USAGI is a Python script designed to automate the process of synthesizing and performing gate-level simulations for digital designs across a range of cycle times.

synthesis digital-design gate-level-simulation nycu iclab nycu-course

Updated Nov 21, 2024
Python

alirezajaberirad / Object-Oriented-Modeling-of-Electronic-Circuits

This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022

image-processing object-oriented systemc object-oriented-programming gate-level system-modeling systemc-ams gate-level-simulation rtl-design

Updated Jul 29, 2022
C++

poshtkohi / pdes

A Parallel Discrete Event Simulation Engine with Examples

software-engineering multi-core partitioning metis conservative many-core discrete-event-simulation sychronization logic-simulator des-simulators queueing-networks pdes gate-level-simulation parallel-simulation parallel-discrete-event-simulation

Updated Oct 15, 2022
C++

Farbod-Siahkali / Digital-Logical-Designs-Projects

Digital Logical Designs Course Projects

state-machine rtl gate-level-simulation rtl-design dld-project

Updated Aug 19, 2022
Verilog

ivop / break6502

6502 gate level simulation in C++

6502 gate-level-simulation

Updated Feb 16, 2024
C++

FarshidKeivanian / Optimization-of-JK-Flip-Flop-Layout-with-Minimal-Average-Power-of-Consumption-based-on-ACOR-Fuzzy-A

FuzzyACOR-Algorithm (Adaptive fuzzy metaheuristic based optimisation algorithm)

Updated May 10, 2022
MATLAB

BhattSoham / RISCV-HDP

Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)

c assembly spike verilog gtkwave soc yosys risc-v iverilog gate-level-simulation hardware-design chipcron

Updated May 8, 2024
Verilog

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