Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB

UART interface to a block ram in the Tang Nano 9k FPGA. No pin connections needed, just use the USB UART.

UART interface to a block ram in the Tang Nano FPGA. No pin connections needed, just use the USB UART.

Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.

Convert binary ROM to Verilog syntax case statement for synthesizing with Lattice Synthesis Engine.