Add support for resharding width-sharded tensors to/from DRAM #15526
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This commit introduces a new width-shard to width-shard reshard kernel, modeled after the height-sharded tensor reshard special case implemented in `reshard_multi_core_same_width`. Supported operations include: - L1 to L1 - L1 to DRAM - DRAM to L1 Currently, only row-major tensors are supported. For unsupported cases, we fall back to the generalized reshard implementation. Unit tests have been added to validate the new kernel functionality.
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Problem description
Resharding a width-sharded tensor from L1 → DRAM is currently not supported.
For context, this type of reshard is required for UNet Shallow's trace+2CQ implementation because the output tensor cannot be persistent in L1 due to size limitations.
The inverse operation (DRAM to L1) will be required for the UNet input tensor preprocessing once
ttnn.convert_to_hwcis implemented.What's changed
test_reshard.py::test_reshardtest_reshard.py::test_dram_reshardtest_reshard.py::test_dram_reshard_with_program_cacheChecklist
tests/tt_eager/python_api_testing/unit_testing/misc/test_reshard.py)