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Reformat code
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luojia65 committed Mar 23, 2022
1 parent 7e9c8d7 commit fb6c239
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Showing 2 changed files with 10 additions and 7 deletions.
12 changes: 6 additions & 6 deletions src/plic.rs
Original file line number Diff line number Diff line change
Expand Up @@ -17,27 +17,27 @@ pub trait PlicExt {
/// Is this M-Mode interrupt enabled on given hart?
fn is_enabled(hart_id: usize, interrupt: Self::Interrupt) -> bool;
/// Enable an interrupt for a given hart
///
///
/// # Safety
///
///
/// May effect normal interrupt handling procedure
unsafe fn unmask(hart_id: usize, interrupt: Self::Interrupt);
/// Disable an interrupt for a given hart
fn mask(hart_id: usize, interrupt: Self::Interrupt);
/// Get global priority for one interrupt
fn get_priority(interrupt: Self::Interrupt) -> Priority;
/// Globally set priority for one interrupt
///
///
/// # Safety
///
///
/// May effect normal interrupt handling procedure
unsafe fn set_priority(interrupt: Self::Interrupt, prio: Priority);
/// Get priority threshold for a given hart
fn get_threshold(hart_id: usize) -> Priority;
/// Set the priority threshold for a given hart
///
///
/// # Safety
///
///
/// May effect normal interrupt handling procedure
unsafe fn set_threshold(hart_id: usize, threshold: Priority);
/// Mark that given hart have claimed to handle this interrupt
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5 changes: 4 additions & 1 deletion src/serial.rs
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,10 @@ impl<UART> Serial<UART> {
Tx { uart: self.uart },
Rx {
// clippy allow: inner marker variable only indicates ownership, does not include actual data
uart: unsafe { #[allow(clippy::uninit_assumed_init)] mem::MaybeUninit::uninit().assume_init() },
uart: unsafe {
#[allow(clippy::uninit_assumed_init)]
mem::MaybeUninit::uninit().assume_init()
},
},
)
}
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