Upgrade the examples to a recent version of riscv.

.cargo/config

@@ -4,7 +4,7 @@
 
 [target.riscv64gc-unknown-none-elf]
 #runner = "riscv64-unknown-elf-gdb -x gdb_init"
-runner = "../k210-run --flash"
+runner = "bash ../k210-run.sh --flash"
 rustflags = [
   "-C", "link-arg=-Tmemory.x",
   "-C", "link-arg=-Tlink.x",

Cargo.toml

@@ -1,11 +1,20 @@
 [package]
 name = "k210-example"
-version = "0.1.1"
+version = "0.3.0"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 edition = "2018"
 
 [dependencies]
 panic-halt = "0.2.0"
-riscv = "0.6.0"
-riscv-rt = "0.8.0"
-k210-hal = "0.2.0"
+riscv = "0.10"
+riscv-rt = "0.11"
+k210-pac = {git = "https://github.com/alexistm/k210-pac", branch = "feature/svd_0_28_0", features = ["critical"]}
+k210-hal = {path = "../k210-hal"}
+# k210-hal = {git = "https://github.com/alexistm/k210-hal", branch = "feature/svd_0_28_0"}
+embedded-hal = "0.2"
+
+[profile.dev]
+panic = "abort"
+
+[profile.release]
+panic = "abort"

README.md

@@ -4,6 +4,16 @@
 
 This project is developed and maintained by the [RISC-V team][team].
 
+## Building
+
+```
+rustup target add riscv64gc-unknown-none-elf
+rustup +nightly target add riscv64gc-unknown-none-elf
+
+cargo build --examples
+cargo +nightly build --examples # for examples with interrupts
+```
+
 ## Getting started
 
 Start openocd:

build.rs

@@ -1,13 +1,15 @@
-use std::{env, fs};
-use std::path::PathBuf;
 use std::io::Write;
+use std::path::PathBuf;
+use std::{env, fs};
 
 fn main() {
     // Put the linker script somewhere the linker can find it
     let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
     println!("cargo:rustc-link-search={}", out_dir.display());
 
-    fs::File::create(out_dir.join("memory.x")).unwrap()
-        .write_all(include_bytes!("memory.x")).unwrap();
+    fs::File::create(out_dir.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
     println!("cargo:rerun-if-changed=memory.x");
 }

examples/blinky.rs

@@ -1,28 +1,46 @@
 #![no_std]
 #![no_main]
 
+use embedded_hal::digital::v2::OutputPin;
+use embedded_hal::digital::v2::ToggleableOutputPin;
+use k210_hal::{fpioa, gpio::Gpio, pac, prelude::*};
 use panic_halt as _;
-use k210_hal::{prelude::*, fpioa, pac, gpio::Gpio};
 
 #[riscv_rt::entry]
 fn main() -> ! {
-    let p = pac::Peripherals::take().unwrap();
-    
+    let p = unsafe { pac::Peripherals::steal() };
+
     let mut sysctl = p.SYSCTL.constrain();
     let fpioa = p.FPIOA.split(&mut sysctl.apb0);
     let gpio = p.GPIO.split(&mut sysctl.apb0);
+
+    let io12 = fpioa.io12.into_function(fpioa::GPIO7);
+    let io13 = fpioa.io13.into_function(fpioa::GPIO5);
     let io14 = fpioa.io14.into_function(fpioa::GPIO6);
+    let mut green = Gpio::new(gpio.gpio7, io12).into_push_pull_output();
+    let mut red = Gpio::new(gpio.gpio5, io13).into_push_pull_output();
     let mut blue = Gpio::new(gpio.gpio6, io14).into_push_pull_output();
 
-    blue.try_set_low().ok();
+    red.set_high().unwrap();
+    green.set_high().unwrap();
+    blue.set_high().unwrap();
 
     let mut last_update = riscv::register::mcycle::read();
+    let mut i = 0;
     loop {
         let cur = riscv::register::mcycle::read();
         if cur - last_update >= 100_000_000 {
             last_update = cur;
 
-            blue.try_toggle().ok();
+            red.toggle().unwrap();
+            if i % 2 == 0 {
+                green.toggle().unwrap();
+            }
+            if i % 3 == 0 {
+                blue.toggle().unwrap();
+            }
+
+            i += 1;
         }
     }
 }

examples/gpio-console.rs

@@ -1,17 +1,17 @@
 #![no_std]
 #![no_main]
 
+use k210_hal::{fpioa, gpio::Gpio, pac, prelude::*, stdout::Stdout};
 use panic_halt as _;
-use k210_hal::{prelude::*, fpioa, pac, gpio::Gpio, stdout::Stdout};
 
 #[riscv_rt::entry]
 fn main() -> ! {
-    let p = pac::Peripherals::take().unwrap();
+    let p = unsafe { pac::Peripherals::steal() };
 
     let mut sysctl = p.SYSCTL.constrain();
     let fpioa = p.FPIOA.split(&mut sysctl.apb0);
     let gpio = p.GPIO.split(&mut sysctl.apb0);
-    let gpiohs = p.GPIOHS.split();
+    let _gpiohs = p.GPIOHS.split();
 
     // Configure clocks (TODO)
     let clocks = k210_hal::clock::Clocks::new();
@@ -20,31 +20,30 @@ fn main() -> ! {
     let _uarths_tx = fpioa.io5.into_function(fpioa::UARTHS_TX);
 
     // let boot_button = Gpio::new(
-    //     gpio.gpio2, 
+    //     gpio.gpio2,
     //     fpioa.io16.into_function(fpioa::GPIO2)
     // ).into_pull_up_input();
     let io14 = fpioa.io14.into_function(fpioa::GPIO6);
-    let mut blue = Gpio::new(gpio.gpio6, io14).into_push_pull_output();
+    let mut _blue = Gpio::new(gpio.gpio6, io14).into_push_pull_output();
 
     // Configure UART
-    let serial = p.UARTHS.configure(
-        115_200.bps(), 
-        &clocks
-    );
+    let serial = p.UARTHS.configure(115_200.bps(), &clocks);
     let (mut tx, _rx) = serial.split();
 
     let mut stdout = Stdout(&mut tx);
 
     writeln!(stdout, "Hello, Rust!").ok();
 
-    unsafe { &*pac::GPIO::ptr() }.source.write(|w| unsafe { w.bits(0xaa) });
+    unsafe { &*pac::GPIO::ptr() }
+        .source
+        .write(|w| unsafe { w.bits(0xaa) });
     loop {
         for i in 8..16 {
             let io = unsafe { &*pac::FPIOA::ptr() }.io[i].read();
-            writeln!(stdout, 
+            writeln!(stdout,
                 "[{}] CH {}, DS {:02X}, OE {}, OEI {}, DO {}, DOI {}, PU {}, PD {}, SL {}, IE {}, IEI {}, DII {}, ST {}, PA {}",
                 i, io.ch_sel().bits(), io.ds().bits(), io.oe_en().bit(), io.oe_inv().bit(),
-                io.do_sel().bit(), io.do_inv().bit(), io.pu().bit(), io.pd().bit(), 
+                io.do_sel().bit(), io.do_inv().bit(), io.pu().bit(), io.pd().bit(),
                 io.sl().bit(), io.ie_en().bit(), io.ie_inv().bit(), io.di_inv().bit(), io.st().bit(), io.pad_di().bit()
             ).ok();
         }
@@ -54,9 +53,11 @@ fn main() -> ! {
         let data_input = unsafe { &*pac::GPIO::ptr() }.data_input.read().bits();
         let sync_level = unsafe { &*pac::GPIO::ptr() }.sync_level.read().bits();
         let id_code = unsafe { &*pac::GPIO::ptr() }.id_code.read().bits();
-        writeln!(stdout, 
+        writeln!(
+            stdout,
             "O {:08b}, D {:08b}, S {:08b}, I {:08b}, SY {:08b}, ID 0x{:08X}",
             data_output, direction, source, data_input, sync_level, id_code
-        ).ok();
+        )
+        .ok();
     }
 }

examples/gpiohs-interrupt.rs

@@ -1,10 +1,17 @@
 #![no_std]
 #![no_main]
 
-use k210_hal::{prelude::*, pac::{self, Interrupt}, plic::*, fpioa, gpiohs::Edge, stdout::Stdout};
-use panic_halt as _;
-use riscv::register::{mie,mstatus,mhartid,mcause};
 use core::sync::atomic::{AtomicBool, Ordering};
+use k210_hal::{
+    fpioa,
+    gpiohs::Edge,
+    pac::{self, Interrupt},
+    plic::*,
+    prelude::*,
+    stdout::Stdout,
+};
+use panic_halt as _;
+use riscv::register::{mcause, mhartid, mie, mstatus};
 
 static INTR: AtomicBool = AtomicBool::new(false);
 
@@ -23,7 +30,7 @@ fn my_trap_handler() {
 
     let irq = pac::PLIC::claim(hart_id).unwrap();
     let prio = pac::PLIC::get_priority(irq);
-    unsafe { 
+    unsafe {
         pac::PLIC::set_threshold(hart_id, prio);
         mie::clear_msoft();
         mie::clear_mtimer();
@@ -35,19 +42,25 @@ fn my_trap_handler() {
 
     let cause = mcause::read().bits();
 
-    writeln!(stdout, 
-        "[Interrupt] Hart #{}, Cause: {:016X}, Edges: {:?}", 
-        hart_id, cause, gpiohs0.check_edges()
-    ).ok();
+    writeln!(
+        stdout,
+        "[Interrupt] Hart #{}, Cause: {:016X}, Edges: {:?}",
+        hart_id,
+        cause,
+        gpiohs0.check_edges()
+    )
+    .ok();
 
-    unsafe { INTR_INFO = Some(IntrInfo { hart_id, cause }); }
+    unsafe {
+        INTR_INFO = Some(IntrInfo { hart_id, cause });
+    }
 
     INTR.store(true, Ordering::SeqCst);
 
     gpiohs0.clear_interrupt_pending_bits();
     // actual handle process ends
 
-    unsafe { 
+    unsafe {
         mie::set_msoft();
         mie::set_mtimer();
         pac::PLIC::set_threshold(hart_id, threshold);
@@ -56,15 +69,15 @@ fn my_trap_handler() {
 }
 
 static mut SHARED_STDOUT: core::mem::MaybeUninit<
-    k210_hal::stdout::Stdout<k210_hal::serial::Tx<pac::UARTHS>>
+    k210_hal::stdout::Stdout<k210_hal::serial::Tx<pac::UARTHS>>,
 > = core::mem::MaybeUninit::uninit();
 static mut GPIOHS0: core::mem::MaybeUninit<
-    k210_hal::gpiohs::Gpiohs0<k210_hal::gpiohs::Input<k210_hal::gpiohs::PullUp>>
+    k210_hal::gpiohs::Gpiohs0<k210_hal::gpiohs::Input<k210_hal::gpiohs::PullUp>>,
 > = core::mem::MaybeUninit::uninit();
 
 #[riscv_rt::entry]
 fn main() -> ! {
-    let p = pac::Peripherals::take().unwrap();
+    let p = unsafe { pac::Peripherals::steal() };
 
     let mut sysctl = p.SYSCTL.constrain();
     let fpioa = p.FPIOA.split(&mut sysctl.apb0);
@@ -93,11 +106,11 @@ fn main() -> ! {
         // Set the Machine-External bit in MIE
         mie::set_mext();
     }
-    
+
     writeln!(stdout, "Enabling interrupt trigger for GPIOHS0").ok();
     boot.trigger_on_edge(Edge::RISING | Edge::FALLING);
 
-    // enable IRQ for gpiohs0 interrupt 
+    // enable IRQ for gpiohs0 interrupt
     writeln!(stdout, "Enabling IRQ for GPIOHS0").ok();
     unsafe {
         pac::PLIC::set_priority(Interrupt::GPIOHS0, Priority::P1);
@@ -106,20 +119,24 @@ fn main() -> ! {
 
     writeln!(stdout, "Configuration finished!").ok();
 
-    loop { 
+    loop {
         writeln!(stdout, "Waiting for interrupt").ok();
-        unsafe { riscv::asm::wfi(); } 
+        unsafe {
+            riscv::asm::wfi();
+        }
 
         while !INTR.load(Ordering::SeqCst) {
             use core::sync::atomic::{self, Ordering};
             atomic::compiler_fence(Ordering::SeqCst);
         }
         INTR.store(false, Ordering::SeqCst);
 
-        writeln!(stdout, 
-            "Interrupt was triggered! hart_id: {}, cause: {:16X}", 
+        writeln!(
+            stdout,
+            "Interrupt was triggered! hart_id: {}, cause: {:16X}",
             unsafe { INTR_INFO }.unwrap().hart_id,
             unsafe { INTR_INFO }.unwrap().cause,
-        ).ok();
+        )
+        .ok();
     }
 }