Dependably fast multi-core in-memory transactions
- Linux x86_64 >= 3.0
- Intel CPU >= Haswell
- Hugepage (2 GiB) support
- g++ >= 5.3
- cmake >= 2.8
- make >= 3.81
- libnuma-dev >= 2.0
- bash >= 4.0
- python >= 3.4
* cd cicada-core/build
* cmake ..
* make -j
* cd cicada-core/build
* ln -s src/mica/test/*.json .
* ../script/setup.sh 16384 16384 # 2 NUMA nodes, 32 Ki pages (64 GiB)
* cd cicada-core/build
* sudo ./test_tx 10000000 16 0.95 0.99 200000 28
- The main namespace is mica for historical reasons. This may change in the future.
- Some code (e.g., memory pool allocation) needs to be modified for many-core (> 64 cores) non-dual-socket systems.
- NUMA-aware parts are tested on a dual-socket system that assigns even-numbered lcore IDs to CPU 0 cores and odd-numbered lcore IDs to CPU 1 cores.
- The system expects a full memory bandwidth configuration (e.g., all 4 channels are active).
- Busy-waiting in contention regulation can be inefficient if hyperthreading is enabled.
- StaticConfig::kPairwiseSleeping can be enabled to reduce wasted cycles on hyperthreading (experimental).
- Backoff is currently using only RDTSC for spinning, which can add an excessive delay upon VM live migration.
Hyeontaek Lim (hl@cs.cmu.edu)
Copyright 2014, 2015, 2016, 2017 Carnegie Mellon University
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