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Releases: raulgilabert/SISA-Custom-Instruction-Assembler

Bug fixes with negative offset on memory instructions

26 Jul 10:56
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Bug fixes:

  • Error raised when trying to preprocess a memory instruction with negative offset

Some other fixes:

  • Deleted extra new lines on translated .S

Basic custom instruction for SISA SIMD ampliation PEC 2024

26 Jul 11:29
cc97b2d
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Support for SIMD instructions of https://github.com/raulgilabert/ampliacio-PEC

  • MVRV
  • MVVR
  • ADDV
  • SUBV
  • SHAV
  • SHLV
  • MULV
  • MULHV
  • MULHUV
  • STV
  • LDV