VHDL implementation of variable bit UP counter.
The counter bits can be varied according to the user.
The bit value should be changed in both the code and testbench file.
The testbech has 2 instances of bit value.
The testbench simulation time is set according to the 8 bit counter, after which the counter resets.
The simulation time should also be changed while changing the bits of counter to see the counter count till max value and reset.
The counter has active high reset, which when made 0 resets the counter.