Repositories list

• GEM5

  Public
  C++

  •

  BSD 3-Clause "New" or "Revised" License

  •27•67•13•9•Updated Dec 3, 2024Dec 3, 2024

• XiangShan

  Public
  Open-source high-performance RISC-V processor

  chiselrisc-vmicroarchitecture

  Scala

  •

  Other

  •668•4.9k•61•45•Updated Dec 3, 2024Dec 3, 2024

• NEMU

  Public
  C

  •

  Other

  •92•237•33•20•Updated Dec 3, 2024Dec 3, 2024

• CPU2006LiteWrapper

  Public
  Makefile

  •2•9•1•2•Updated Dec 3, 2024Dec 3, 2024

• ChiselAIA

  Public
  RISC-V AIA in Chisel

  chiselriscvinterrupt+ 1aia

  Scala

  •

  Mulan Permissive Software License, Version 2

  •0•4•10•1•Updated Dec 3, 2024Dec 3, 2024

• riscv-isa-sim

  Public
  Spike, a RISC-V ISA Simulator

  C

  •

  Other

  •864•5•0•3•Updated Dec 3, 2024Dec 3, 2024

• nexus-am

  Public
  C

  •27•31•5•3•Updated Dec 3, 2024Dec 3, 2024

• difftest

  Public
  Modern co-simulation framework for RISC-V CPUs

  C++

  •

  Mulan Permissive Software License, Version 2

  •68•120•7•8•Updated Dec 3, 2024Dec 3, 2024

• ready-to-run

  Public
  Shell

  •8•4•3•0•Updated Dec 3, 2024Dec 3, 2024

• CoupledL2

  Public
  Open-source non-blocking L2 cache

  Scala

  •

  Other

  •20•33•0•5•Updated Dec 3, 2024Dec 3, 2024

• riscv-hyp-tests

  Public
  A bare-metal application to test specific features of the risc-v hypervisor extension

  C

  •

  GNU General Public License v3.0

  •22•1•0•0•Updated Dec 3, 2024Dec 3, 2024

• llvm-project

  Public
  The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

  LLVM

  •

  Other

  •12k•0•0•0•Updated Dec 3, 2024Dec 3, 2024

• tl-test-new

  Public
  The Unified TileLink Memory Subsystem Tester for XiangShan

  C++

  •

  Mulan Permissive Software License, Version 2

  •1•2•0•0•Updated Dec 2, 2024Dec 2, 2024

• OpenLLC

  Public
  Scala

  •

  Other

  •3•3•0•0•Updated Dec 2, 2024Dec 2, 2024

• Utility

  Public
  Scala

  •16•7•0•6•Updated Dec 2, 2024Dec 2, 2024

• Deterload

  Public
  Xiangshan deterministic workloads generator

  nixcheckpointdeterministic+ 5workloadsworkloadcheckpointsxiangshansimpoint

  Nix

  •

  Mulan Permissive Software License, Version 2

  •2•9•2•0•Updated Nov 29, 2024Nov 29, 2024

• rocket-chip

  Public
  Rocket Chip Generator

  Scala

  •

  Other

  •1.1k•4•0•0•Updated Nov 29, 2024Nov 29, 2024

• YunSuan

  Public
  This repo includes XiangShan's function units

  Scala

  •

  Mulan Permissive Software License, Version 2

  •11•15•0•0•Updated Nov 29, 2024Nov 29, 2024

• XiangShan-doc

  Public
  Documentation for XiangShan

  TeX

  •

  Creative Commons Attribution 4.0 International

  •136•353•5•2•Updated Nov 28, 2024Nov 28, 2024

• env-scripts

  Public
  Scripts for XiangShan

  Verilog

  •14•11•0•0•Updated Nov 28, 2024Nov 28, 2024

• nemu_board

  Public
  Shell

  •0•1•0•0•Updated Nov 25, 2024Nov 25, 2024

• HuanCun

  Public
  Open-source high-performance non-blocking cache

  Scala

  •

  Other

  •35•68•2•1•Updated Nov 21, 2024Nov 21, 2024

• gos

  Public
  Assembly

  •2•3•0•0•Updated Nov 19, 2024Nov 19, 2024

• XiangShan-home

  Public
  Creative Commons Attribution 4.0 International

  •0•0•0•0•Updated Nov 12, 2024Nov 12, 2024

• riscv-rootfs

  Public
  C

  •10•1•0•2•Updated Nov 8, 2024Nov 8, 2024

• xfuzz

  Public
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers

  Scala

  •

  Other

  •1•12•2•0•Updated Nov 8, 2024Nov 8, 2024

• CPU2017LiteWrapper

  Public
  Makefile

  •0•1•0•0•Updated Nov 7, 2024Nov 7, 2024

• xs-env

  Public
  XiangShan Frontend Develop Environment

  Shell

  •

  Other

  •48•47•2•1•Updated Nov 2, 2024Nov 2, 2024

• OpenNCB

  Public
  Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

  buschiselchisel3+ 5socaxi4amba-axiamba-chiprotocol-bridge

  Scala

  •0•1•0•0•Updated Oct 31, 2024Oct 31, 2024

• riscv-tests

  Public
  C

  •

  Other

  •465•0•0•1•Updated Oct 30, 2024Oct 30, 2024