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FPGA Addon Custom Device

The FPGA Addon Custom Device allows users to access an existing FPGA bitfile in VeriStand with little or no modification. The FPGA bitfile does not need to use the standard VeriStand FPGA framework (in that it does not require two DMA channels and an XML descriptor file). It also provides support for streaming data over DMA to a VeriStand waveform.

The add-on requires an IRQ (address of 30) to fire on the FPGA before it starts.

The add-on does not provide a way to synchronize data acquisition/generation with the VeriStand Primary Control Loop (PCL), and it does not support using the FPGA as a timing source for the PCL. Both of these features are supported in the standard VeriStand FPGA framework.

Using the Custom Device

LabVIEW Source Code Version

LabVIEW 2020

Dependencies

Running the custom device

Developing or building from source

Git History & Rebasing Policy

Branch rebasing and other history modifications will be listed here, with several notable exceptions:

  • Branches prefixed with dev/ may be rebased, overwritten, or deleted at any time.
  • Pull requests may be squashed on merge.

License

The FPGA Addon Custom Device is licensed under an MIT-style license (see LICENSE). Other incorporated projects may be licensed under different licenses. All licenses allow for non-commercial and commercial use.