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Merge pull request #164 from nanocoh/main
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  testing loading verilog with prims
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nanocoh authored Nov 28, 2024
2 parents 03fce28 + 7866341 commit bba428b
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Showing 2 changed files with 86 additions and 52 deletions.
93 changes: 43 additions & 50 deletions src/najaeda/najaeda/netlist.py
Original file line number Diff line number Diff line change
Expand Up @@ -455,6 +455,12 @@ class Top:
def __init__(self):
self.design = snl.SNLUniverse.get().getTopDesign()

def __str__(self):
return str(self.design)

def __eq__(self, other):
return self.design == other.design

def get_child_instance(self, name: str):
return Instance(snl.SNLPath(), self.design.getInstance(name))

Expand All @@ -464,16 +470,16 @@ def get_child_instances(self):
yield Instance(path, inst)

def create_child_instance(self, model, name):
design = getTop().design
design = get_top().design
newSNLInstance = snl.SNLInstance.create(design, model, name)
path = snl.SNLPath(self.path, newSNLInstance)
return Instance(path, newSNLInstance)

def delete_instance(self, name: str):
getTop().design.getInstance(name).destroy()
get_top().design.getInstance(name).destroy()

def create_output_term(self, name: str) -> InstTerm:
design = getTop().design
design = get_top().design
newSNLTerm = snl.SNLScalarTerm.create(
design,
snl.SNLTerm.Direction.Output,
Expand All @@ -482,7 +488,7 @@ def create_output_term(self, name: str) -> InstTerm:
return TopTerm(newSNLTerm)

def create_input_term(self, name: str) -> InstTerm:
design = getTop().design
design = get_top().design
newSNLTerm = snl.SNLScalarTerm.create(
design,
snl.SNLTerm.Direction.Input,
Expand All @@ -496,10 +502,7 @@ def create_output_bus_term(
width: int,
offset: int
) -> list:
uniq = snl.SNLUniquifier(self.path)
uniq_path = uniq.getPathUniqCollection()
self.inst = tuple(uniq_path)[len(tuple(uniq_path)) - 1]
design = self.inst.getModel()
design = get_top().design
newSNLTerm = snl.SNLBusTerm.create(
design,
snl.SNLTerm.Direction.Output,
Expand All @@ -509,23 +512,15 @@ def create_output_bus_term(
)
instTerms = []
for i in range(width):
instTerms.append(
TopTerm(
self.path,
self.inst.getInstTerm(newSNLTerm.getBit(i))
)
)
instTerms.append(TopTerm(newSNLTerm.getBit(i)))
return instTerms

def create_input_bus_term(
self, name: str,
width: int,
offset: int
) -> list:
uniq = snl.SNLUniquifier(self.path)
uniq_path = uniq.getPathUniqCollection()
self.inst = tuple(uniq_path)[len(tuple(uniq_path)) - 1]
design = self.inst.getModel()
design = get_top().design
newSNLTerm = snl.SNLBusTerm.create(
design,
snl.SNLTerm.Direction.Input,
Expand All @@ -535,55 +530,53 @@ def create_input_bus_term(
)
instTerms = []
for i in range(width):
instTerms.append(
InstTerm(
self.path,
self.inst.getInstTerm(newSNLTerm.getBit(i))
)
)
instTerms.append(TopTerm(newSNLTerm.getBit(i)))
return instTerms

def create_net(self, name: str) -> Net:
uniq = snl.SNLUniquifier(self.path)
uniq_path = uniq.getPathUniqCollection()
self.inst = tuple(uniq_path)[len(tuple(uniq_path)) - 1]
design = self.inst.getModel()
design = get_top().design
newSNLNet = snl.SNLScalarNet.create(design, name)
return Net(self.path, newSNLNet)
return Net(snl.SNLPath(), newSNLNet)

def create_bus_net(self, name: str, width: int, offset: int) -> list:
uniq = snl.SNLUniquifier(self.path)
uniq_path = uniq.getPathUniqCollection()
self.inst = tuple(uniq_path)[len(tuple(uniq_path)) - 1]
design = self.inst.getModel()
design = get_top().design
newSNLNet = snl.SNLBusNet.create(design, width, offset, name)
list = []
for i in range(width):
list.append(Net(self.path, newSNLNet.getBit(i)))
list.append(Net(snl.SNLPath(), newSNLNet.getBit(i)))
return list

def get_term_list_for_bus(self, name: str) -> list:
list = []
bus = self.inst.getModel().getBusTerm(name)
bus = self.design.getBusTerm(name)
for bit in bus.getBits():
list.append(InstTerm(self.path, self.inst.getInstTerm(bit)))
list.append(TopTerm(bit))
return list

def get_net(self, name: str) -> Net:
for term in self.inst.getInstTerms():
if term.getBitTerm().getName() == name:
return Net(self.path, term.getNet())
if self.design.getNet(name) is not None:
return Net(snl.SNLPath(), self.design.getNet(name))
return None

def get_net_list_for_bus(self, name: str) -> list:
list = []
bus = self.inst.getModel().getBusNet(name)
bus = self.design.getBusNet(name)
for bit in bus.getBits():
list.append(Net(self.path, bit))
list.append(Net(snl.SNLPath(), bit))
return list

def get_input_terms(self):
for term in self.design.getBitTerms():
if term.getDirection() == snl.SNLTerm.Direction.Input:
yield TopTerm(term)

def get_output_terms(self):
for term in self.design.getBitTerms():
if term.getDirection() == snl.SNLTerm.Direction.Output:
yield TopTerm(term)


def getTopDB() -> snl.SNLDB:
def get_top_db() -> snl.SNLDB:
if snl.SNLUniverse.get() is None:
snl.SNLUniverse.create()
if snl.SNLUniverse.get().getTopDB() is None:
Expand All @@ -592,13 +585,13 @@ def getTopDB() -> snl.SNLDB:
return snl.SNLUniverse.get().getTopDB()


def getTop():
def get_top():
return Top()


def createTop():
def create_top():
# init
db = getTopDB()
db = get_top_db()
# create top design
lib = snl.SNLLibrary.create(db)
top = snl.SNLDesign.create(lib)
Expand All @@ -607,18 +600,18 @@ def createTop():


def load_verilog(files: list):
getTopDB().loadVerilog(files)
return getTop()
get_top_db().loadVerilog(files)
return get_top()


def load_liberty(files: list):
getTopDB().loadLibertyPrimitives(files)
get_top_db().loadLibertyPrimitives(files)


def get_primitives_library() -> snl.SNLLibrary:
lib = getTopDB().getLibrary("PRIMS")
lib = get_top_db().getLibrary("PRIMS")
if lib is None:
lib = snl.SNLLibrary.createPrimitives(getTopDB())
lib = snl.SNLLibrary.createPrimitives(get_top_db())
return lib


Expand Down
45 changes: 43 additions & 2 deletions test/najaeda/test_najaeda_netlist.py
Original file line number Diff line number Diff line change
Expand Up @@ -32,13 +32,34 @@ def tearDown(self):
snl.SNLUniverse.get().destroy()

def test_loader(self):
print("loader test")
design_files = [os.path.join(verilog_benchmarks, "test0.v")]
primitives = [os.path.join(liberty_benchmarks, "asap7_excerpt" , "test0.lib")]
netlist.load_liberty(primitives)
netlist.load_verilog(design_files)
print(netlist.get_top())
for inst in netlist.get_all_primitive_instances():
print(inst)
if snl.SNLUniverse.get():
snl.SNLUniverse.get().destroy()

def test_loader1(self):
print("loader test")
design_files = [os.path.join(verilog_benchmarks, "test1.v")]
lut4 = snl.SNLDesign.createPrimitive(netlist.get_primitives_library(), "LUT4")
i0 = snl.SNLScalarTerm.create(lut4, snl.SNLTerm.Direction.Input, "I0")
i1 = snl.SNLScalarTerm.create(lut4, snl.SNLTerm.Direction.Input, "I1")
i2 = snl.SNLScalarTerm.create(lut4, snl.SNLTerm.Direction.Input, "I2")
i3 = snl.SNLScalarTerm.create(lut4, snl.SNLTerm.Direction.Input, "I3")
q = snl.SNLScalarTerm.create(lut4, snl.SNLTerm.Direction.Output, "Q")
snl.SNLParameter.create_binary(lut4, "INIT", 16, 0x0000)
netlist.load_verilog(design_files)
for inst in netlist.get_all_primitive_instances():
print(inst)
if snl.SNLUniverse.get():
snl.SNLUniverse.get().destroy()


def test_instance(self):
u = snl.SNLUniverse.create()
db = snl.SNLDB.create(u)
Expand Down Expand Up @@ -286,8 +307,28 @@ def testInstTerm(self):
self.assertFalse(instTerm0.is_output())




def testTop(self):
netlist.create_top()
top = netlist.get_top()
self.assertIsNotNone(top)
self.assertTrue(top == netlist.get_top())
top.create_input_term("I0")
top.create_input_bus_term("I1", 4, 0)
top.create_output_term("O")
count = 0
for input in top.get_input_terms():
count += 1
self.assertTrue(count == 6)
count = 0
for output in top.get_output_terms():
count += 1
self.assertTrue(count == 1)
busList = top.get_term_list_for_bus("I1")
self.assertTrue(len(busList) == 5)
top.create_net("netI1")
self.assertIsNotNone(top.get_net("netI1"))
top.create_bus_net("netI1bus", 4, 0)
self.assertIsNotNone(len(top.get_net_list_for_bus("netI1bus")) == 5)

if __name__ == '__main__':
faulthandler.enable()
Expand Down

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