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Update Makefile
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xtofalex authored May 2, 2024
1 parent 6d749ed commit a975d40
Showing 1 changed file with 3 additions and 3 deletions.
6 changes: 3 additions & 3 deletions designs/arm_core/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -24,19 +24,19 @@ arm_core_netlist.v: src/arm_core.v

arm_core_snl/snl.mf: arm_core_netlist.v
export PYTHONPATH=${SET_PYTHONPATH}; \
${PYTHON_ENV} ${NAJA_EDIT} -f verilog -t snl -i $< -o arm_core_snl -p ${PRIMITIVES}
${PYTHON_ENV} ${NAJA_EDIT} -f verilog -t snl -i $< -o arm_core_snl -p ${PRIMITIVES}/xilinx.py

edges.list: arm_core_snl/snl.mf gen_edge_list.py
export PYTHONPATH=${SET_PYTHONPATH}; \
${NAJA_EDIT} -f snl -i arm_core_snl -e gen_edge_list.py

arm_core_snl.v primitives.v: arm_core_netlist.v
export PYTHONPATH=${SET_PYTHONPATH}; \
${NAJA_EDIT} -f verilog -t verilog -p ${PRIMITIVES} -i arm_core_netlist.v -o arm_core_snl.v -d primitives.v
${NAJA_EDIT} -f verilog -t verilog -p ${PRIMITIVES}/xilinx.py -i arm_core_netlist.v -o arm_core_snl.v -d primitives.v

arm_core_snl_error.v: arm_core_netlist.v src/add_error.py
export PYTHONPATH=${SET_PYTHONPATH}; \
${NAJA_EDIT} -e src/add_error.py -f verilog -t verilog -p ${PRIMITIVES} -i arm_core_netlist.v -o arm_core_snl_error.v -d primitives.v
${NAJA_EDIT} -e src/add_error.py -f verilog -t verilog -p ${PRIMITIVES}/xilinx.py -i arm_core_netlist.v -o arm_core_snl_error.v -d primitives.v

clean:
-rm arm_core_snl.v primitives.v arm_core_netlist.v

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