[ibex,dv] Add inject_intg_err task for mem buses

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>

dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv

@@ -10,6 +10,7 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
 
   ibex_mem_intf_seq_item item;
   mem_model              m_mem;
+  bit                    enable_intg_error = 1'b0;
   bit                    enable_error = 1'b0;
   // Used to ensure that whenever inject_error() is called, the very next transaction will inject an
   // error, and that enable_error will not be flipped back to 0 immediately
@@ -64,6 +65,7 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
       // TODO: Parametrize this. Until then, this needs to be changed manually.
       if (aligned_addr == 32'h8ffffff8) begin
         req.error = 1'b0;
+        enable_intg_error = 1'b0;
       end
       if (req.error) begin
         `DV_CHECK_STD_RANDOMIZE_FATAL(rand_data)
@@ -90,7 +92,10 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
 
       // If data_was_uninitialized is true then we want to force bad integrity bits: invert the
       // correct ones, which we know will break things for the codes we use.
-      if (data_was_uninitialized) req.intg = ~req.intg;
+      if (data_was_uninitialized || enable_intg_error) begin
+        req.intg = ~req.intg;
+        enable_intg_error = 1'b0;
+      end
 
       `uvm_info(get_full_name(), $sformatf("Response transfer:\n%0s", req.sprint()), UVM_HIGH)
       start_item(req);
@@ -111,6 +116,10 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
     this.enable_error = 1'b1;
   endfunction
 
+  virtual function void inject_intg_error();
+    this.enable_intg_error = 1'b1;
+  endfunction
+
   virtual function bit get_error_synch();
     return this.error_synch;
   endfunction

dv/uvm/core_ibex/env/core_ibex_env_cfg.sv

@@ -4,6 +4,7 @@
 
 class core_ibex_env_cfg extends uvm_object;
 
+  bit                           enable_mem_intg_err;
   bit                           enable_irq_single_seq;
   bit                           enable_irq_multiple_seq;
   bit                           enable_irq_nmi_seq;
@@ -18,6 +19,7 @@ class core_ibex_env_cfg extends uvm_object;
   rand scrambling_key_agent_cfg scrambling_key_cfg;
 
   `uvm_object_utils_begin(core_ibex_env_cfg)
+    `uvm_field_int(enable_mem_intg_err,   UVM_DEFAULT)
     `uvm_field_int(enable_irq_single_seq,   UVM_DEFAULT)
     `uvm_field_int(enable_irq_multiple_seq,   UVM_DEFAULT)
     `uvm_field_int(enable_irq_nmi_seq,   UVM_DEFAULT)
@@ -33,6 +35,7 @@ class core_ibex_env_cfg extends uvm_object;
 
   function new(string name = "");
     super.new(name);
+    void'($value$plusargs("enable_mem_intg_err=%0d", enable_mem_intg_err));
     void'($value$plusargs("enable_irq_single_seq=%0d", enable_irq_single_seq));
     void'($value$plusargs("enable_irq_multiple_seq=%0d", enable_irq_multiple_seq));
     void'($value$plusargs("enable_irq_nmi_seq=%0d", enable_irq_nmi_seq));

dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml

@@ -549,6 +549,25 @@
     +suppress_pmp_setup=1
   rtl_test: core_ibex_mem_error_test
   sim_opts: >
+    +enable_mem_intg_err=0
+    +require_signature_addr=1
+  compare_opts:
+    compare_final_value_only: 1
+
+- test: riscv_mem_intg_error_test
+  description: >
+    Normal random instruction test, but randomly insert memory load/store integrity errors
+  iterations: 15
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +require_signature_addr=1
+    +instr_cnt=10000
+    +randomize_csr=1
+    +enable_unaligned_load_store=1
+    +suppress_pmp_setup=1
+  rtl_test: core_ibex_mem_error_test
+  sim_opts: >
+    +enable_mem_intg_err=1
     +require_signature_addr=1
   compare_opts:
     compare_final_value_only: 1

dv/uvm/core_ibex/tb/core_ibex_tb_top.sv

@@ -158,8 +158,9 @@ module core_ibex_tb_top;
   );
 
   // We should never see any alerts triggered in normal testing
-  `ASSERT(NoAlertsTriggered,
+  `ASSERT(NoAlertsTriggered_A,
     !dut_if.alert_minor && !dut_if.alert_major_internal && !dut_if.alert_major_bus, clk, !rst_n)
+  `DV_ASSERT_CTRL("NoAlertsTriggered", core_ibex_tb_top.NoAlertsTriggered_A)
 
   // Data load/store vif connection
   assign data_mem_vif.reset = ~rst_n;

dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv

@@ -205,6 +205,13 @@ class memory_error_seq extends core_base_new_seq#(ibex_mem_intf_seq_item);
   bit                          start_seq = 0; // Use this bit to start any unique sequence once
 
   rand error_type_e            err_type = PickErr;
+  rand bit                     inject_intg_err;
+  // CONTROL_KNOB: Configure the rate between seeing an integrity error versus seeing a bus error.
+  int unsigned                 intg_err_pct = 50;
+  constraint inject_intg_err_c {
+     inject_intg_err dist {1 :/ intg_err_pct,
+                           0 :/ 100 - intg_err_pct};
+  }
 
   `uvm_object_utils(memory_error_seq)
   `uvm_declare_p_sequencer(core_ibex_vseqr)
@@ -214,21 +221,39 @@ class memory_error_seq extends core_base_new_seq#(ibex_mem_intf_seq_item);
   endfunction
 
   virtual task send_req();
-    case (err_type)
-      IsideErr: begin
+    `DV_CHECK_MEMBER_RANDOMIZE_FATAL(inject_intg_err)
+    // If we expect to see only bus errors, we can enable this assertion. Otherwise
+    // integrity errors would cause alerts to trigger.
+    `DV_ASSERT_CTRL_REQ("NoAlertsTriggered", intg_err_pct == 0)
+    case ({err_type, inject_intg_err})
+      {IsideErr, 1'b0}: begin
         vseq.instr_intf_seq.inject_error();
       end
-      DsideErr: begin
+      {DsideErr, 1'b0}: begin
         vseq.data_intf_seq.inject_error();
       end
-      PickErr: begin
+      {PickErr, 1'b0}: begin
         `DV_CHECK_STD_RANDOMIZE_FATAL(choose_side)
         if (choose_side) begin
           vseq.instr_intf_seq.inject_error();
         end else begin
           vseq.data_intf_seq.inject_error();
         end
       end
+      {IsideErr, 1'b1}: begin
+        vseq.instr_intf_seq.inject_intg_error();
+      end
+      {DsideErr, 1'b1}: begin
+        vseq.data_intf_seq.inject_intg_error();
+      end
+      {PickErr, 1'b1}: begin
+        `DV_CHECK_STD_RANDOMIZE_FATAL(choose_side)
+        if (choose_side) begin
+          vseq.instr_intf_seq.inject_intg_error();
+        end else begin
+          vseq.data_intf_seq.inject_intg_error();
+        end
+      end
       default: begin
         // DO nothing
       end

dv/uvm/core_ibex/tests/core_ibex_test_lib.sv

@@ -1174,6 +1174,8 @@ class core_ibex_mem_error_test extends core_ibex_directed_test;
     memory_error_seq_h = memory_error_seq::type_id::create("memory_error_seq_h", this);
     `uvm_info(`gfn, "Running core_ibex_mem_error_test", UVM_LOW)
     memory_error_seq_h.vseq = vseq;
+    memory_error_seq_h.iteration_modes = InfiniteRuns;
+    memory_error_seq_h.intg_err_pct = cfg.enable_mem_intg_err ? 75 : 0;
     fork
       begin
         // Wait for the hart to initialize