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[clang][Driver] Add HIPAMD Driver support for AMDGCN flavoured SPIR-V #95061

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Jun 25, 2024
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662f160
Add initial support for AMDGCN flavoured SPIRV.
AlexVlx Apr 23, 2024
393ce66
Fix formatting.
AlexVlx Apr 23, 2024
2a10ad0
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Apr 25, 2024
98db8f7
Use `fillAMDGPUFeatureMap` instead of copy-pasta.
AlexVlx Apr 25, 2024
c359e0a
Add `__has_builtin` test.
AlexVlx Apr 25, 2024
e98f3f5
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Apr 28, 2024
c41726d
Re-use `AMDGPUTargetInfo`, where feasible, instead of copypasta-ing.
AlexVlx Apr 28, 2024
4698b58
Incorporate review suggestions.
AlexVlx Apr 28, 2024
aa1cd7c
Fix header ordering.
AlexVlx Apr 28, 2024
f9729ef
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 8, 2024
8257cb1
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 9, 2024
900cd69
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 11, 2024
3307f17
Handle `wavefrontsize` (we need both 32 and 64); add more tests.
AlexVlx May 12, 2024
eee6063
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 13, 2024
d2f4244
Add an additional test.
AlexVlx May 14, 2024
4cb4026
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 14, 2024
84a621d
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 14, 2024
1841385
AMDGCN SPIRV should allow both AMDGCN and SPIRV builtins.
AlexVlx May 15, 2024
0ce2da3
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 15, 2024
120b73c
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 15, 2024
f3942bd
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 15, 2024
31ac77d
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 15, 2024
0e9b1a1
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 16, 2024
83cd5e0
Enable AMDGCN flavoured SPIRV in the experimental SPIRV BE.
AlexVlx May 16, 2024
e9158b0
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 16, 2024
05074e7
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 19, 2024
e1fb93f
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 20, 2024
36c4bf6
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 27, 2024
5ffa186
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 27, 2024
cf1880c
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx May 29, 2024
4d85a1b
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 5, 2024
516e14c
Revert spurios testing noise, AMDGCN SPIRV is still SPIRV.
AlexVlx Jun 5, 2024
bdc3eb5
First pass at updating SPIR-V docs to reflect the addition of AMDGCN …
AlexVlx Jun 6, 2024
361d47b
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 6, 2024
b088c72
Fix erroneous versioning claim.
AlexVlx Jun 6, 2024
e85b557
Remove function pointer tests.
AlexVlx Jun 6, 2024
1d41787
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 6, 2024
8bcf2b2
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 10, 2024
9b3275b
Add HIP Driver support for AMDGCN flavoured SPIRV.
AlexVlx Jun 10, 2024
5b764ec
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 10, 2024
ba3fb6f
Fix formatting.
AlexVlx Jun 10, 2024
3719c3b
Revert changing the HIPAMD default to SPIR-V; tweak some tests.
AlexVlx Jun 12, 2024
7ca1c87
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 13, 2024
f3e5145
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 17, 2024
089bb9b
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 18, 2024
b60e753
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 19, 2024
8741e7c
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 20, 2024
5f775b8
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 20, 2024
4aa60c7
Fix warning.
AlexVlx Jun 20, 2024
1c2d0fa
Fix broken test.
AlexVlx Jun 20, 2024
e8a78a2
Reorder check.
AlexVlx Jun 21, 2024
294cd9c
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 21, 2024
f712c53
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 22, 2024
fe927e0
Do not allow mixing SPIR-V & concrete `offload-arch`s for now.
AlexVlx Jun 22, 2024
5ce5497
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 22, 2024
2220d37
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 24, 2024
83ec34c
Merge branch 'main' of https://github.com/llvm/llvm-project into amdg…
AlexVlx Jun 24, 2024
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1 change: 1 addition & 0 deletions clang/include/clang/Basic/Cuda.h
Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,7 @@ enum class CudaArch {
GFX12_GENERIC,
GFX1200,
GFX1201,
AMDGCNSPIRV,
Generic, // A processor model named 'generic' if the target backend defines a
// public one.
LAST,
Expand Down
1 change: 1 addition & 0 deletions clang/lib/Basic/Cuda.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -148,6 +148,7 @@ static const CudaArchToStringMap arch_names[] = {
{CudaArch::GFX12_GENERIC, "gfx12-generic", "compute_amdgcn"},
GFX(1200), // gfx1200
GFX(1201), // gfx1201
{CudaArch::AMDGCNSPIRV, "amdgcnspirv", "compute_amdgcn"},
{CudaArch::Generic, "generic", ""},
// clang-format on
};
Expand Down
1 change: 1 addition & 0 deletions clang/lib/Basic/Targets/NVPTX.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -232,6 +232,7 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
case CudaArch::GFX12_GENERIC:
case CudaArch::GFX1200:
case CudaArch::GFX1201:
case CudaArch::AMDGCNSPIRV:
case CudaArch::Generic:
case CudaArch::LAST:
break;
Expand Down
1 change: 1 addition & 0 deletions clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3541,6 +3541,7 @@ void CGOpenMPRuntimeGPU::processRequiresDirective(
case CudaArch::GFX12_GENERIC:
case CudaArch::GFX1200:
case CudaArch::GFX1201:
case CudaArch::AMDGCNSPIRV:
case CudaArch::Generic:
case CudaArch::UNUSED:
case CudaArch::UNKNOWN:
Expand Down
3 changes: 2 additions & 1 deletion clang/lib/CodeGen/CodeGenModule.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -907,7 +907,8 @@ void CodeGenModule::Release() {
if (Context.getTargetInfo().getTriple().isWasm())
EmitMainVoidAlias();

if (getTriple().isAMDGPU()) {
if (getTriple().isAMDGPU() ||
(getTriple().isSPIRV() && getTriple().getVendor() == llvm::Triple::AMD)) {
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I'm wondering if we should add isAMD to llvm::Triple or something.

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I didn't know the vendor got used for anything.

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I'm wondering if we should add isAMD to llvm::Triple or something.

We do have isAMDGCN, but that reflects the Arch. I guess it might be convenient sugar to have a predicate on vendors as well? I don't find the manual check excessively offensive FWIW.

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I didn't know the vendor got used for anything.

This matches how we've documented it when we added the AMDGCN flavoured SPIR-V, and seemed to reflect the idea that this is SPIRV(64) with customisations for AMD as the vendor; do you think it is or can become problematic?

// Emit amdhsa_code_object_version module flag, which is code object version
// times 100.
if (getTarget().getTargetOpts().CodeObjectVersion !=
Expand Down
26 changes: 20 additions & 6 deletions clang/lib/Driver/Driver.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -147,6 +147,14 @@ getNVIDIAOffloadTargetTriple(const Driver &D, const ArgList &Args,
static std::optional<llvm::Triple>
getHIPOffloadTargetTriple(const Driver &D, const ArgList &Args) {
if (!Args.hasArg(options::OPT_offload_EQ)) {
auto OffloadArchs = Args.getAllArgValues(options::OPT_offload_arch_EQ);
if (llvm::find(OffloadArchs, "amdgcnspirv") != OffloadArchs.cend()) {
if (OffloadArchs.size() == 1)
return llvm::Triple("spirv64-amd-amdhsa");
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Use a toolchain with spirv64 as triple will cause trouble for us to support mixed amdgcn and spirv fat binaries, which is critical for us.

Better to take the approach similar to #75357, i.e. treat spirv as a processor of amgcn triple, so that we can use HIPAMD toolchain for both spirv and real amdgcn processor.

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Thanks for the pointer, much appreciated! I will revisit this/take your suggestion, but for the initial experimental support it was deemed acceptable to carry this temporary limitation (unless you strongly object, of course).

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I am OK to commit this since the command line option won't change so users are not affected.

// Mixing specific & SPIR-V compilation is not supported for now.
D.Diag(diag::err_drv_only_one_offload_target_supported);
return std::nullopt;
}
return llvm::Triple("amdgcn-amd-amdhsa"); // Default HIP triple.
}
auto TT = getOffloadTargetTriple(D, Args);
Expand Down Expand Up @@ -3247,10 +3255,14 @@ class OffloadingActionBuilder final {
// supported GPUs. sm_20 code should work correctly, if
// suboptimally, on all newer GPUs.
if (GpuArchList.empty()) {
if (ToolChains.front()->getTriple().isSPIRV())
GpuArchList.push_back(CudaArch::Generic);
else
if (ToolChains.front()->getTriple().isSPIRV()) {
if (ToolChains.front()->getTriple().getVendor() == llvm::Triple::AMD)
GpuArchList.push_back(CudaArch::AMDGCNSPIRV);
else
GpuArchList.push_back(CudaArch::Generic);
} else {
GpuArchList.push_back(DefaultCudaArch);
}
}

return Error;
Expand Down Expand Up @@ -6517,9 +6529,11 @@ const ToolChain &Driver::getOffloadingDeviceToolChain(
// things.
switch (TargetDeviceOffloadKind) {
case Action::OFK_HIP: {
if (Target.getArch() == llvm::Triple::amdgcn &&
Target.getVendor() == llvm::Triple::AMD &&
Target.getOS() == llvm::Triple::AMDHSA)
if (((Target.getArch() == llvm::Triple::amdgcn ||
Target.getArch() == llvm::Triple::spirv64) &&
Target.getVendor() == llvm::Triple::AMD &&
Target.getOS() == llvm::Triple::AMDHSA) ||
!Args.hasArgNoClaim(options::OPT_offload_EQ))
TC = std::make_unique<toolchains::HIPAMDToolChain>(*this, Target,
HostTC, Args);
else if (Target.getArch() == llvm::Triple::spirv64 &&
Expand Down
4 changes: 3 additions & 1 deletion clang/lib/Driver/ToolChains/Clang.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4939,7 +4939,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
CmdArgs.push_back(Args.MakeArgString(NormalizedTriple));

if (JA.isDeviceOffloading(Action::OFK_HIP) &&
getToolChain().getTriple().isAMDGPU()) {
(getToolChain().getTriple().isAMDGPU() ||
(getToolChain().getTriple().isSPIRV() &&
getToolChain().getTriple().getVendor() == llvm::Triple::AMD))) {
// Device side compilation printf
if (Args.getLastArg(options::OPT_mprintf_kind_EQ)) {
CmdArgs.push_back(Args.MakeArgString(
Expand Down
45 changes: 43 additions & 2 deletions clang/lib/Driver/ToolChains/HIPAMD.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
#include "AMDGPU.h"
#include "CommonArgs.h"
#include "HIPUtility.h"
#include "SPIRV.h"
#include "clang/Basic/Cuda.h"
#include "clang/Basic/TargetID.h"
#include "clang/Driver/Compilation.h"
Expand Down Expand Up @@ -193,6 +194,33 @@ void AMDGCN::Linker::constructLldCommand(Compilation &C, const JobAction &JA,
Lld, LldArgs, Inputs, Output));
}

// For SPIR-V the inputs for the job are device AMDGCN SPIR-V flavoured bitcode
// and the output is either a compiled SPIR-V binary or bitcode (-emit-llvm). It
// calls llvm-link and then the llvm-spirv translator. Once the SPIR-V BE will
// be promoted from experimental, we will switch to using that. TODO: consider
// if we want to run any targeted optimisations over IR here, over generic
// SPIR-V.
void AMDGCN::Linker::constructLinkAndEmitSpirvCommand(
Compilation &C, const JobAction &JA, const InputInfoList &Inputs,
const InputInfo &Output, const llvm::opt::ArgList &Args) const {
assert(!Inputs.empty() && "Must have at least one input.");

constructLlvmLinkCommand(C, JA, Inputs, Output, Args);

// Linked BC is now in Output

// Emit SPIR-V binary.
llvm::opt::ArgStringList TrArgs{
"--spirv-max-version=1.6",
"--spirv-ext=+all",
"--spirv-allow-extra-diexpressions",
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@AlexVlx nit: if generation of NonSemantic.Shader.DebugInfo.200 is turned on - this option is not needed as the extended instruction already adds all DWARF expressions (including LLVM-specific expressions).

"--spirv-allow-unknown-intrinsics",
"--spirv-lower-const-expr",
"--spirv-preserve-auxdata",
"--spirv-debug-info-version=nonsemantic-shader-200"};
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Recently I've found this patch in gitlog and was intrigued, does this line mean, that AMD driver supports KhronosGroup/SPIRV-Registry#186 ? Just for my curiosity. It may also make me push the instruction set for ratification sooner :)

SPIRV::constructTranslateCommand(C, *this, JA, Output, Output, TrArgs);
}

// For amdgcn the inputs of the linker job are device bitcode and output is
// either an object file or bitcode (-emit-llvm). It calls llvm-link, opt,
// llc, then lld steps.
Expand All @@ -214,6 +242,9 @@ void AMDGCN::Linker::ConstructJob(Compilation &C, const JobAction &JA,
if (JA.getType() == types::TY_LLVM_BC)
return constructLlvmLinkCommand(C, JA, Inputs, Output, Args);

if (getToolChain().getTriple().isSPIRV())
return constructLinkAndEmitSpirvCommand(C, JA, Inputs, Output, Args);

return constructLldCommand(C, JA, Inputs, Output, Args);
}

Expand Down Expand Up @@ -270,6 +301,13 @@ void HIPAMDToolChain::addClangTargetOptions(
CC1Args.push_back("-fapply-global-visibility-to-externs");
}

// For SPIR-V we embed the command-line into the generated binary, in order to
// retrieve it at JIT time and be able to do target specific compilation with
// options that match the user-supplied ones.
if (getTriple().isSPIRV() &&
!DriverArgs.hasArg(options::OPT_fembed_bitcode_marker))
CC1Args.push_back("-fembed-bitcode=marker");

for (auto BCFile : getDeviceLibs(DriverArgs)) {
CC1Args.push_back(BCFile.ShouldInternalize ? "-mlink-builtin-bitcode"
: "-mlink-bitcode-file");
Expand Down Expand Up @@ -303,7 +341,8 @@ HIPAMDToolChain::TranslateArgs(const llvm::opt::DerivedArgList &Args,
}

Tool *HIPAMDToolChain::buildLinker() const {
assert(getTriple().getArch() == llvm::Triple::amdgcn);
assert(getTriple().getArch() == llvm::Triple::amdgcn ||
getTriple().getArch() == llvm::Triple::spirv64);
return new tools::AMDGCN::Linker(*this);
}

Expand Down Expand Up @@ -358,7 +397,9 @@ VersionTuple HIPAMDToolChain::computeMSVCVersion(const Driver *D,
llvm::SmallVector<ToolChain::BitCodeLibraryInfo, 12>
HIPAMDToolChain::getDeviceLibs(const llvm::opt::ArgList &DriverArgs) const {
llvm::SmallVector<BitCodeLibraryInfo, 12> BCLibs;
if (DriverArgs.hasArg(options::OPT_nogpulib))
if (DriverArgs.hasArg(options::OPT_nogpulib) ||
(getTriple().getArch() == llvm::Triple::spirv64 &&
getTriple().getVendor() == llvm::Triple::AMD))
return {};
ArgStringList LibraryPaths;

Expand Down
4 changes: 4 additions & 0 deletions clang/lib/Driver/ToolChains/HIPAMD.h
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,10 @@ class LLVM_LIBRARY_VISIBILITY Linker final : public Tool {
const InputInfoList &Inputs,
const InputInfo &Output,
const llvm::opt::ArgList &Args) const;
void constructLinkAndEmitSpirvCommand(Compilation &C, const JobAction &JA,
const InputInfoList &Inputs,
const InputInfo &Output,
const llvm::opt::ArgList &Args) const;
};

} // end namespace AMDGCN
Expand Down
3 changes: 3 additions & 0 deletions clang/test/Driver/cuda-arch-translation.cu
Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,8 @@
// RUN: | FileCheck -check-prefixes=HIP,GFX900 %s
// RUN: %clang -x hip -### --target=x86_64-linux-gnu -c --cuda-gpu-arch=gfx902 -nogpuinc -nogpulib %s 2>&1 \
// RUN: | FileCheck -check-prefixes=HIP,GFX902 %s
// RUN: %clang -x hip -### --target=x86_64-linux-gnu -c --cuda-gpu-arch=amdgcnspirv -nogpuinc -nogpulib %s 2>&1 \
// RUN: | FileCheck -check-prefixes=HIP,SPIRV %s

// CUDA: ptxas
// CUDA-SAME: -m64
Expand Down Expand Up @@ -95,3 +97,4 @@
// GFX810:-targets=host-x86_64-unknown-linux,hipv4-amdgcn-amd-amdhsa--gfx810
// GFX900:-targets=host-x86_64-unknown-linux,hipv4-amdgcn-amd-amdhsa--gfx900
// GFX902:-targets=host-x86_64-unknown-linux,hipv4-amdgcn-amd-amdhsa--gfx902
// SPIRV:-targets=host-x86_64-unknown-linux,hip-spirv64-amd-amdhsa--amdgcnspirv
3 changes: 3 additions & 0 deletions clang/test/Frontend/embed-bitcode.ll
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,9 @@
; RUN: %clang_cc1 -triple aarch64 -emit-llvm \
; RUN: -fembed-bitcode=all -x ir %s -o - \
; RUN: | FileCheck %s -check-prefix=CHECK-ELF
; RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm \
; RUN: -fembed-bitcode=all -x ir %s -o - \
; RUN: | FileCheck %s -check-prefix=CHECK-ELF

; check .bc input
; RUN: %clang_cc1 -triple thumbv7-apple-ios8.0.0 -emit-llvm-bc \
Expand Down
2 changes: 1 addition & 1 deletion clang/test/Misc/target-invalid-cpu-note.c
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@

// RUN: not %clang_cc1 -triple nvptx--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix NVPTX
// NVPTX: error: unknown target CPU 'not-a-cpu'
// NVPTX-NEXT: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, sm_35, sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72, sm_75, sm_80, sm_86, sm_87, sm_89, sm_90, sm_90a, gfx600, gfx601, gfx602, gfx700, gfx701, gfx702, gfx703, gfx704, gfx705, gfx801, gfx802, gfx803, gfx805, gfx810, gfx9-generic, gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, gfx941, gfx942, gfx10-1-generic, gfx1010, gfx1011, gfx1012, gfx1013, gfx10-3-generic, gfx1030, gfx1031, gfx1032, gfx1033, gfx1034, gfx1035, gfx1036, gfx11-generic, gfx1100, gfx1101, gfx1102, gfx1103, gfx1150, gfx1151, gfx1152, gfx12-generic, gfx1200, gfx1201{{$}}
// NVPTX-NEXT: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, sm_35, sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72, sm_75, sm_80, sm_86, sm_87, sm_89, sm_90, sm_90a, gfx600, gfx601, gfx602, gfx700, gfx701, gfx702, gfx703, gfx704, gfx705, gfx801, gfx802, gfx803, gfx805, gfx810, gfx9-generic, gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, gfx941, gfx942, gfx10-1-generic, gfx1010, gfx1011, gfx1012, gfx1013, gfx10-3-generic, gfx1030, gfx1031, gfx1032, gfx1033, gfx1034, gfx1035, gfx1036, gfx11-generic, gfx1100, gfx1101, gfx1102, gfx1103, gfx1150, gfx1151, gfx1152, gfx12-generic, gfx1200, gfx1201, amdgcnspirv{{$}}

// RUN: not %clang_cc1 -triple r600--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix R600
// R600: error: unknown target CPU 'not-a-cpu'
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5309,6 +5309,8 @@ static const char *getSectionNameForBitcode(const Triple &T) {
llvm_unreachable("GOFF is not yet implemented");
break;
case Triple::SPIRV:
if (T.getVendor() == Triple::AMD)
return ".llvmbc";
llvm_unreachable("SPIRV is not yet implemented");
break;
case Triple::XCOFF:
Expand All @@ -5334,6 +5336,8 @@ static const char *getSectionNameForCommandline(const Triple &T) {
llvm_unreachable("GOFF is not yet implemented");
break;
case Triple::SPIRV:
if (T.getVendor() == Triple::AMD)
return ".llvmcmd";
llvm_unreachable("SPIRV is not yet implemented");
break;
case Triple::XCOFF:
Expand Down