added CV32RT fastirq summary/analysis

XTeic.adoc

@@ -1,7 +1,7 @@
 
 = XTeic
 Jan Oleksiewicz <jnk0le@hotmail.com>
-:appversion: 0.34.2
+:appversion: 0.34.3
 :toc:
 :toclevels: 5
 :sectnums:
@@ -95,6 +95,20 @@ NOTE: according to <<clicentrycycles>>, handler entry time is 6 cycles on sifive
 NOTE: BTW, my prediction is that the "competitor A" will be able to do a
 "comparison against riscv" without resorting to FUD tactics, right after CLIC is ratified
 
+Typical interrupt latency of CLIC trampoline was measured at 33 (inline handler) and 42 
+(trampoline) cycles for CV32E40P <<CV32RT>>.
+
+==== CV32RT fastirq
+
+CV32RT "fastirq" <<CV32RT>> extends CLIC by moving prologue handling entirely into
+the hardware as well as introducing background lazy stacking from a shadow register set.
+
+The epilogue is still handled in software.
+
+Tail chaining is supported by `emret` instruction, but a late arrival (higher priority) will have to 
+wait for the background stacking to finish.
+As a consequence there is a jitter equal to the stacking window.
+
 ==== emb-riscv
 
 emb-riscv <<embriscv>> is clean sheet design that attempts to be universal solution
@@ -2239,4 +2253,5 @@ high frequency interrupts which can be handled by `teic.wfi.n4ign` instead.
 * [[[llvmregmaskattr, 49]]] https://lists.llvm.org/pipermail/cfe-dev/2016-July/050022.html
 * [[[clichwswvectoring, 50]]] https://github.com/riscv/riscv-fast-interrupt/issues/314
 * [[[spruge6b, 51]]] https://e2echina.ti.com/cfs-file/__key/communityserver-discussions-components-files/56/5504.2803x-CLA-_2800_1_2900_.pdf
-* [[[spracw5a, 52]]] https://www.ti.com/lit/an/spracw5a/spracw5a.pdf
+* [[[spracw5a, 52]]] https://www.ti.com/lit/an/spracw5a/spracw5a.pdf
+* [[[CV32RT, 53]]] https://arxiv.org/pdf/2311.08320