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change dcd_dcache_*() API return type from void to bool #2887

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merged 1 commit into from
Nov 25, 2024
Merged

change dcd_dcache_*() API return type from void to bool #2887

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10 changes: 3 additions & 7 deletions src/common/tusb_mcu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -364,19 +364,15 @@
#define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep

#define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 64

#if defined(CFG_TUD_DWC2_DMA_ENABLE) && CFG_TUD_DWC2_DMA_ENABLE == 1
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
#endif

#if defined(CFG_TUH_DWC2_DMA_ENABLE) && CFG_TUH_DWC2_DMA_ENABLE == 1
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
#endif

#define CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT 64
#define CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT 64
#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 0

#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif

#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)
#if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421))
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24 changes: 22 additions & 2 deletions src/common/tusb_types.h
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Expand Up @@ -35,8 +35,9 @@
extern "C" {
#endif

#define TUD_EPBUF_DCACHE_SIZE(_size) \
(CFG_TUD_MEM_DCACHE_ENABLE ? (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size))
//------------- Device DCache declaration -------------//
#define TUD_EPBUF_DCACHE_SIZE(_size) (CFG_TUD_MEM_DCACHE_ENABLE ? \
(TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size))

// Declare an endpoint buffer with uint8_t[size]
#define TUD_EPBUF_DEF(_name, _size) \
Expand All @@ -52,6 +53,25 @@
uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
};

//------------- Host DCache declaration -------------//
#define TUH_EPBUF_DCACHE_SIZE(_size) (CFG_TUH_MEM_DCACHE_ENABLE ? \
(TU_DIV_CEIL(_size, CFG_TUH_MEM_DCACHE_LINE_SIZE) * CFG_TUH_MEM_DCACHE_LINE_SIZE) : (_size))

// Declare an endpoint buffer with uint8_t[size]
#define TUH_EPBUF_DEF(_name, _size) \
union { \
CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
};

// Declare an endpoint buffer with a type
#define TUH_EPBUF_TYPE_DEF(_name, _type) \
union { \
CFG_TUH_MEM_ALIGN _type _name; \
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
};


/*------------------------------------------------------------------*/
/* CONSTANTS
*------------------------------------------------------------------*/
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6 changes: 3 additions & 3 deletions src/device/dcd.h
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Expand Up @@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) {

// clean/flush data cache: write cache -> memory.
// Required before an DMA TX transfer to make sure data is in memory
void dcd_dcache_clean(const void* addr, uint32_t data_size);
bool dcd_dcache_clean(const void* addr, uint32_t data_size);

// invalidate data cache: mark cache as invalid, next read will read from memory
// Required BOTH before and after an DMA RX transfer
void dcd_dcache_invalidate(const void* addr, uint32_t data_size);
bool dcd_dcache_invalidate(const void* addr, uint32_t data_size);

// clean and invalidate data cache
// Required before an DMA transfer where memory is both read/write by DMA
void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);
bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);

//--------------------------------------------------------------------+
// Controller API
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9 changes: 6 additions & 3 deletions src/device/usbd.c
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Expand Up @@ -97,16 +97,19 @@ TU_ATTR_WEAK void dcd_disconnect(uint8_t rhport) {
(void) rhport;
}

TU_ATTR_WEAK void dcd_dcache_clean(const void* addr, uint32_t data_size) {
TU_ATTR_WEAK bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
return true;
}

TU_ATTR_WEAK void dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
TU_ATTR_WEAK bool dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
return true;
}

TU_ATTR_WEAK void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
TU_ATTR_WEAK bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
return true;
}

//--------------------------------------------------------------------+
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30 changes: 8 additions & 22 deletions src/portable/chipidea/ci_hs/dcd_ci_hs.c
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Expand Up @@ -34,43 +34,29 @@
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
#include "ci_hs_imxrt.h"

void dcd_dcache_clean(void const* addr, uint32_t data_size) {
imxrt_dcache_clean(addr, data_size);
bool dcd_dcache_clean(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean(addr, data_size);
}

void dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
imxrt_dcache_invalidate(addr, data_size);
bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
return imxrt_dcache_invalidate(addr, data_size);
}

void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
imxrt_dcache_clean_invalidate(addr, data_size);
bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
return imxrt_dcache_clean_invalidate(addr, data_size);
}

#else

#if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
#include "ci_hs_lpc18_43.h"

#elif TU_CHECK_MCU(OPT_MCU_MCXN9)
// MCX N9 only port 1 use this controller
#include "ci_hs_mcx.h"

#else
#error "Unsupported MCUs"
#endif

TU_ATTR_WEAK void dcd_dcache_clean(void const* addr, uint32_t data_size) {
(void) addr; (void) data_size;
}

TU_ATTR_WEAK void dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
(void) addr; (void) data_size;
}

TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
(void) addr; (void) data_size;
}
#endif

//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
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21 changes: 9 additions & 12 deletions src/portable/synopsys/dwc2/dcd_dwc2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -83,22 +83,19 @@ CFG_TUD_MEM_SECTION static struct {
// DMA
//--------------------------------------------------------------------
#if CFG_TUD_MEM_DCACHE_ENABLE
void dcd_dcache_clean(const void* addr, uint32_t data_size) {
if (addr && data_size) {
dwc2_dcache_clean(addr, data_size);
}
bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
TU_VERIFY(addr && data_size);
return dwc2_dcache_clean(addr, data_size);
}

void dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
if (addr && data_size) {
dwc2_dcache_invalidate(addr, data_size);
}
bool dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
TU_VERIFY(addr && data_size);
return dwc2_dcache_invalidate(addr, data_size);
}

void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
if (addr && data_size) {
dwc2_dcache_clean_invalidate(addr, data_size);
}
bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
TU_VERIFY(addr && data_size);
return dwc2_dcache_clean_invalidate(addr, data_size);
}
#endif

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12 changes: 6 additions & 6 deletions src/portable/synopsys/dwc2/dwc2_esp32.h
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Expand Up @@ -130,22 +130,22 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_
return size;
}

TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean(const void* addr, uint32_t data_size) {
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean(const void* addr, uint32_t data_size) {
const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M;
data_size = round_up_to_cache_line_size(data_size);
assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
return ESP_OK == esp_cache_msync((void*)addr, data_size, flag);
}

TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_invalidate(const void* addr, uint32_t data_size) {
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_invalidate(const void* addr, uint32_t data_size) {
const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C;
data_size = round_up_to_cache_line_size(data_size);
assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
return ESP_OK == esp_cache_msync((void*)addr, data_size, flag);
}

TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C;
data_size = round_up_to_cache_line_size(data_size);
assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
return ESP_OK == esp_cache_msync((void*)addr, data_size, flag);
}

#endif
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20 changes: 10 additions & 10 deletions src/tusb_option.h
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Original file line number Diff line number Diff line change
Expand Up @@ -397,6 +397,14 @@
#define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4)
#endif

#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE
#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#endif

#define CFG_TUSB_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
#endif

// OS selection
#ifndef CFG_TUSB_OS
#define CFG_TUSB_OS OPT_OS_NONE
Expand Down Expand Up @@ -433,11 +441,7 @@
#endif

#ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE
#ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT
#define CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#endif

#define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT
#define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
#endif

#ifndef CFG_TUD_ENDPOINT0_SIZE
Expand Down Expand Up @@ -556,11 +560,7 @@
#endif

#ifndef CFG_TUH_MEM_DCACHE_LINE_SIZE
#ifndef CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT
#define CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT 32
#endif

#define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT
#define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
#endif

//------------- CLASS -------------//
Expand Down
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