Fix VHDL backend code for older compilers.

grame-cncm · Aug 13, 2023 · cf639f5 · cf639f5
1 parent 62a0c2b
commit cf639f5
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Showing 3 changed files with 12 additions and 10 deletions.
diff --git a/compiler/generator/vhdl/vhdl_code_container.cpp b/compiler/generator/vhdl/vhdl_code_container.cpp
@@ -127,7 +127,8 @@ std::ostream& operator<<(std::ostream& out, const VhdlCodeContainer& container)
         out << "\t\t" << "clock => ap_clk," << std::endl;
         out << "\t\t" << "reset => ap_rst_n," << std::endl;
 
-        auto source = register_series.source.has_value() ? container._signal_identifier.at(register_series.source.value()) : "ap_start";
+        auto source = register_series.source.has_value() ? container._signal_identifier.at(*register_series.source) : "ap_start";
+
         out << "\t\t" << "data_in => " << source << "," << std::endl;
         out << "\t\t" << "data_out => registers_" << register_id << std::endl;
         out << '\t' << ");" << std::endl << std::endl;
@@ -208,7 +209,7 @@ void VhdlCodeContainer::register_component(const Vertex& component, std::optiona
         // For recursive outputs, we generate a one-sample delay as well
         // as a series of registers from ap_start to the write_enable signal
         // of the storage medium
-        generateOneSampleDelay(component.node_hash, sig_type, cycles_from_input.value());
+        generateOneSampleDelay(component.node_hash, sig_type, *cycles_from_input);
     } else if (isSigOutput(sig, &i, x)) {
         // Normal outputs do not generate anything
     } else if (isSigDelay1(sig, x)) {

diff --git a/compiler/generator/vhdl/vhdl_producer.cpp b/compiler/generator/vhdl/vhdl_producer.cpp
@@ -132,25 +132,26 @@ void VhdlProducer::normalize()
 {
     // For each vertex `v`, we find the weight `w` of the longest incoming path.
     // The notion of weight is defined here as the sum of pipeline stages of vertices along the path.
-    std::vector<std::optional<int>> max_incoming_weight = std::vector(_vertices.size(), std::optional<int>());
+    std::vector<std::optional<int>> max_incoming_weight(_vertices.size(), std::optional<int>());
+
     auto transposed_graph = transposedGraph();
 
     std::function<int(int)> incoming_weight;
     incoming_weight = [&](int vertex) {
         if (max_incoming_weight[vertex].has_value()) {
-            return max_incoming_weight[vertex].value();
+            return *max_incoming_weight[vertex];
         }
 
         max_incoming_weight[vertex] = std::make_optional(0);
 
         for (auto edge : transposed_graph[vertex]) {
             int w = incoming_weight(edge.target);
-            if (w > max_incoming_weight[vertex].value()) {
-                max_incoming_weight[vertex].value() = w;
+            if (w > *max_incoming_weight[vertex]) {
+                *max_incoming_weight[vertex] = w;
             }
         }
         max_incoming_weight[vertex] = std::make_optional(_vertices[vertex].pipeline_stages + max_incoming_weight[vertex].value_or(0));
-        return max_incoming_weight[vertex].value();
+        return *max_incoming_weight[vertex];
     };
 
     for (size_t i = 0; i < _vertices.size(); ++i) {
@@ -161,7 +162,7 @@ void VhdlProducer::normalize()
     // to `u -> v` to compensate for the lag.
     for (size_t u = 0; u < _vertices.size(); ++u) {
         for (Edge& edge : _edges[u]) {
-            int max_pipeline_stages = max_incoming_weight[edge.target].value() - _vertices[edge.target].pipeline_stages;
+            int max_pipeline_stages = *max_incoming_weight[edge.target] - _vertices[edge.target].pipeline_stages;
             edge.register_count += max_pipeline_stages - _vertices[u].pipeline_stages;
         }
     }
@@ -189,7 +190,7 @@ void VhdlProducer::retiming()
         // Otherwise, we search for the other half
         auto retiming = findRetiming(m);
         if (retiming.has_value()) {
-            best_retiming = retiming.value();
+            best_retiming = *retiming;
             r = m - 1;
         } else {
             l = m + 1;

diff --git a/compiler/generator/vhdl/vhdl_producer.hh b/compiler/generator/vhdl/vhdl_producer.hh
@@ -249,7 +249,7 @@ class VhdlProducer : public SignalVisitor {
     }
 
     std::vector<std::vector<Edge>> transposedGraph() const {
-        std::vector<std::vector<Edge>> transposed = std::vector(_edges.size(), std::vector<Edge>());
+        std::vector<std::vector<Edge>> transposed(_edges.size(), std::vector<Edge>());
         for (size_t v = 0; v < _edges.size(); ++v) {
             for (auto edge : _edges[v]) {
                 transposed[edge.target].push_back(Edge(v, edge.register_count, edge.critical_path_delay));