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DSLX DMA: Draft implementation
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Signed-off-by: Michal Czyz <mczyz@antmicro.com>
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@mczyz-antmicro
mczyz-antmicro committed Feb 8, 2024
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# Copyright 2023 The XLS Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

load(
"//xls/build_rules:xls_build_defs.bzl",
"xls_dslx_fmt_test",
"xls_dslx_ir",
"xls_dslx_library",
"xls_dslx_test",
"xls_ir_opt_ir",
"xls_ir_verilog",
)

package(
default_applicable_licenses = ["//:license"],
default_visibility = ["//xls:xls_users"],
licenses = ["notice"],
)

# Common
xls_dslx_library(
name = "dma_common",
srcs = [
"bus/axi_pkg.x",
"bus/axi_st_pkg.x",
"common.x",
"config.x",
"gpf.x",
],
)

xls_dslx_test(
name = "test_common",
library = "dma_common",
)

# CSR
xls_dslx_library(
name = "csr",
srcs = [
"csr.x",
],
deps = [
":dma_common",
],
)

xls_dslx_test(
name = "test_csr",
library = "csr",
)

xls_dslx_ir(
name = "ir_csr_8_32_14",
dslx_top = "csr_8_32_14",
ir_file = "csr_8_32_14.ir",
library = "csr",
)

xls_ir_opt_ir(
name = "opt_ir_csr_8_32_14",
src = "csr_8_32_14.ir",
top = "__csr__csr_8_32_14__CSR_0__8_32_14_next",
)

xls_ir_verilog(
name = "verilog_csr",
src = ":opt_ir_csr_8_32_14.opt.ir",
codegen_args = {
"module_name": "csr",
"delay_model": "unit",
"pipeline_stages": "2",
"reset": "rst",
"use_system_verilog": "false",
},
verilog_file = "csr.v",
)

# AXI CSR
xls_dslx_library(
name = "axi_csr",
srcs = [
"axi_csr.x",
],
deps = [
":csr",
":dma_common",
],
)

xls_dslx_test(
name = "test_axi_csr",
library = "axi_csr",
)

xls_dslx_ir(
name = "axi_csr_8_32_14_ir",
dslx_top = "axi_csr_8_32_14",
ir_file = "axi_csr_8_32_14.ir",
library = "axi_csr",
)

xls_ir_opt_ir(
name = "axi_csr_8_32_14_opt_ir",
src = "axi_csr_8_32_14.ir",
top = "__axi_csr__axi_csr_8_32_14__axi_csr_0__8_32_4_14_4_next",
)

xls_ir_verilog(
name = "verilog_axi_csr",
src = ":axi_csr_8_32_14_opt_ir.opt.ir",
codegen_args = {
"module_name": "axi_csr",
"delay_model": "unit",
"pipeline_stages": "4",
"reset": "rst",
"use_system_verilog": "false",
},
verilog_file = "axi_csr.v",
)

# FIFO
xls_dslx_library(
name = "fifo",
srcs = [
"fifo.x",
],
deps = [
":dma_common",
"//xls/examples:ram_dslx",
],
)

xls_dslx_test(
name = "test_fifo",
library = "fifo",
)

# xls_dslx_ir(
# name = "fifo_ir",
# dslx_top = "fifo_synth",
# ir_file = "fifo_ir.ir",
# library = "fifo",
# )

# xls_ir_opt_ir(
# name = "fifo_ir_opt",
# src = "fifo_ir.ir",
# # FIXME: Top level is not correctly generated in verilog
# top = "__fifo__fifo_synth__FIFO__Writer_0__4_8_1_1_16_1_next"
# )

# xls_ir_verilog(
# name = "verilog_fifo",
# src = ":fifo_ir_opt.opt.ir",
# codegen_args = {
# "module_name": "fifo",
# "delay_model": "unit",
# "pipeline_stages": "3",
# "worst_case_throughput": "2",
# "reset": "rst",
# "use_system_verilog": "false",
# # TODO: setup configuration for RAM macro generation
# # https://google.github.io/xls/codegen_options/#rams-experimental
# # https://github.com/google/xls/blob/609a7ab89d96d2a7396d2418d00d30e4cb57b119/xls/codegen/ram_configuration.h#L99
# # https://github.com/google/xls/blob/609a7ab89d96d2a7396d2418d00d30e4cb57b119/docs_src/tutorials/xlscc_memory.md?plain=1#L140
# },
# verilog_file = "fifo.v",
# )

# Address Generator
xls_dslx_library(
name = "address_generator_lib",
srcs = [
"address_generator.x",
],
deps = [
":dma_common",
],
)

xls_dslx_test(
name = "test_address_generator",
library = "address_generator_lib",
)

# Frontend Reader
xls_dslx_library(
name = "frontend_reader_lib",
srcs = [
"frontend_reader.x",
],
deps = [
":dma_common",
],
)

xls_dslx_test(
name = "test_frontend_reader",
library = "frontend_reader_lib",
)

# Frontend writer
xls_dslx_library(
name = "frontend_writer_lib",
srcs = [
"frontend_writer.x",
],
deps = [
":dma_common",
],
)

xls_dslx_test(
name = "test_frontend_writer",
library = "frontend_writer_lib",
)

# Main controller
xls_dslx_library(
name = "main_controller_lib",
srcs = [
"main_controller.x",
],
deps = [
":address_generator_lib",
":axi_csr",
":dma_common",
":frontend_reader_lib",
":frontend_writer_lib",
],
)

xls_dslx_test(
name = "test_main_controller",
library = "main_controller_lib",
)

# Formatting
xls_dslx_fmt_test(
name = "fmt_address_generator",
src = "address_generator.x",
)

xls_dslx_fmt_test(
name = "fmt_axi_csr",
src = "axi_csr.x",
)

xls_dslx_fmt_test(
name = "fmt_common",
src = "common.x",
)

xls_dslx_fmt_test(
name = "fmt_config",
src = "config.x",
)

xls_dslx_fmt_test(
name = "fmt_csr",
src = "csr.x",
)

xls_dslx_fmt_test(
name = "fmt_fifo",
src = "fifo.x",
)

xls_dslx_fmt_test(
name = "fmt_frontend_reader",
src = "frontend_reader.x",
)

xls_dslx_fmt_test(
name = "fmt_frontend_writer",
src = "frontend_writer.x",
)

xls_dslx_fmt_test(
name = "fmt_gpf",
src = "gpf.x",
)

xls_dslx_fmt_test(
name = "fmt_main_controller",
src = "main_controller.x",
)

xls_dslx_fmt_test(
name = "fmt_bus_axi_pkg",
src = "bus/axi_pkg.x",
)

xls_dslx_fmt_test(
name = "fmt_bus_axi_st_pkg",
src = "bus/axi_st_pkg.x",
)
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