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Format with dslx_fmt
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Signed-off-by: Michal Czyz <mczyz@antmicro.com>
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@mczyz-antmicro
mczyz-antmicro committed Dec 14, 2023
1 parent ab964ce commit 89c11af
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Showing 5 changed files with 266 additions and 372 deletions.
194 changes: 83 additions & 111 deletions xls/modules/axi4/dma/axi_csr.x
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Original file line number Diff line number Diff line change
Expand Up @@ -55,11 +55,11 @@ pub struct axi_r_t<ID_W: u32, DATA_W: u32> {
rlast: uN[1],
}

pub struct axi_csr_state <ADDR_W: u32, DATA_W: u32>{
pub struct axi_csr_state<ADDR_W: u32, DATA_W: u32> {
waddr: uN[ADDR_W],
wdata: uN[DATA_W],
raddr: uN[ADDR_W],
rdata: uN[DATA_W]
rdata: uN[DATA_W],
}

// AXI4 subordinate receives AXI4 transactions and translates them into simple
Expand All @@ -68,62 +68,51 @@ proc axi_csr<ID_W: u32, ADDR_W: u32, DATA_W: u32, STRB_W: u32, REGS_N: u32> {
aw_ch: chan<axi_aw_t<ID_W, ADDR_W>> in;
w_ch: chan<axi_w_t<DATA_W, STRB_W>> in;
b_ch: chan<axi_b_t<ID_W>> out;
ar_ch: chan<axi_ar_t<ID_W, ADDR_W>>in;
r_ch: chan<axi_r_t<ID_W, DATA_W>>out;

read_req: chan<csr::ReadReq<ADDR_W>> out;
read_resp: chan<csr::ReadResp<DATA_W>> in;
write_req: chan<csr::WriteReq<ADDR_W, DATA_W>> out;
ar_ch: chan<axi_ar_t<ID_W, ADDR_W>> in;
r_ch: chan<axi_r_t<ID_W, DATA_W>> out;
read_req: chan<csr::ReadReq<ADDR_W>> out;
read_resp: chan<csr::ReadResp<DATA_W>> in;
write_req: chan<csr::WriteReq<ADDR_W, DATA_W>> out;
write_resp: chan<csr::WriteResp> in;
all_csr: chan<csr::AllCSR<DATA_W,REGS_N>> out;

config(aw_ch: chan<axi_aw_t<ID_W, ADDR_W>> in,
w_ch: chan<axi_w_t<DATA_W, STRB_W>> in,
b_ch: chan<axi_b_t<ID_W>> out,
ar_ch: chan<axi_ar_t<ID_W, ADDR_W>>in,
r_ch: chan<axi_r_t<ID_W, DATA_W>>out,
all_csr: chan<csr::AllCSR<DATA_W,REGS_N>> out
) {
all_csr: chan<csr::AllCSR<DATA_W, REGS_N>> out;

config(aw_ch: chan<axi_aw_t<ID_W, ADDR_W>> in, w_ch: chan<axi_w_t<DATA_W, STRB_W>> in, b_ch
:
chan<axi_b_t<ID_W>> out,
ar_ch: chan<axi_ar_t<ID_W, ADDR_W>> in, r_ch: chan<axi_r_t<ID_W, DATA_W>> out, all_csr
:
chan<csr::AllCSR<DATA_W, REGS_N>> out) {
let (read_req_s, read_req_r) = chan<csr::ReadReq<ADDR_W>>;
let (read_resp_s, read_resp_r) = chan<csr::ReadResp<DATA_W>>;
let (write_req_s, write_req_r) = chan<csr::WriteReq<ADDR_W, DATA_W>>;
let (write_resp_s, write_resp_r) = chan<csr::WriteResp>;

spawn csr::CSR<ADDR_W, DATA_W, REGS_N>(read_req_r, read_resp_s, write_req_r, write_resp_s, all_csr);
spawn csr::CSR<ADDR_W, DATA_W, REGS_N>(
read_req_r, read_resp_s, write_req_r, write_resp_s, all_csr);
(
aw_ch, w_ch, b_ch, ar_ch, r_ch,
read_req_s, read_resp_r, write_req_s,write_resp_r,
all_csr
aw_ch, w_ch, b_ch, ar_ch, r_ch, read_req_s, read_resp_r, write_req_s, write_resp_r,
all_csr,
)
}

init { axi_csr_state<ADDR_W, DATA_W>{
waddr: uN[ADDR_W]:0,
wdata: uN[DATA_W]:0,
raddr: uN[ADDR_W]:0,
rdata: uN[DATA_W]:0
} }
init {
axi_csr_state<ADDR_W, DATA_W> {
waddr: uN[ADDR_W]:0, wdata: uN[DATA_W]:0, raddr: uN[ADDR_W]:0, rdata: uN[DATA_W]:0
}
}

next(tok: token, state: axi_csr_state<ADDR_W, DATA_W>) {
// AW Channel Handler
let (tok, aw_payload, aw_valid) = recv_non_blocking(tok, aw_ch, zero!<axi_aw_t>());
let w_addr = if( aw_valid ) {
aw_payload.awaddr
} else {
state.waddr
};
let w_addr = if aw_valid { aw_payload.awaddr } else { state.waddr };

// W channel Handler
let (tok, w_payload, w_valid) = recv_non_blocking(tok, w_ch, zero!<axi_w_t>());
let w_data = if( w_valid ) {
w_payload.wdata
} else {
state.wdata
};
let w_data = if w_valid { w_payload.wdata } else { state.wdata };

// Handle write to CSR
let tok = send_if(tok, write_req, w_valid, csr::WriteWordReq(w_addr, w_data));
let (tok, _, csr_write_valid) = recv_non_blocking(tok, write_resp, csr::WriteResp{});
let (tok, _, csr_write_valid) = recv_non_blocking(tok, write_resp, csr::WriteResp {});

// B Channel Handlers
let b_msg = axi_b_t { bresp: axi_pkg::AXI_WRITE_RESPONSE_CODES::OKAY, bid: uN[ID_W]:0 };
Expand All @@ -132,78 +121,59 @@ proc axi_csr<ID_W: u32, ADDR_W: u32, DATA_W: u32, STRB_W: u32, REGS_N: u32> {
// AR Channel Handler
// TODO: #984, zero! does not work
let zero_axi_ar_t = axi_ar_t {
arid : uN[ID_W]:0,
araddr : uN[ADDR_W]:0,
arregion : uN[4]:0,
arlen : uN[8]:0,
arsize : axi_pkg::AXI_AXSIZE_ENCODING::MAX_1B_TRANSFER,
arburst : axi_pkg::AXI_AXBURST_ENCODING::FIXED,
arcache : axi_pkg::AXI_ARCACHE_ENCODING::DEV_NO_BUF,
arprot : uN[3]:0,
arqos : uN[4]:0,
};
let (tok, ar_payload, ar_valid) = recv_non_blocking(tok, ar_ch, zero_axi_ar_t);
let r_addr = if( ar_valid ) {
ar_payload.araddr
} else {
state.raddr
arid: uN[ID_W]:0,
araddr: uN[ADDR_W]:0,
arregion: uN[4]:0,
arlen: uN[8]:0,
arsize: axi_pkg::AXI_AXSIZE_ENCODING::MAX_1B_TRANSFER,
arburst: axi_pkg::AXI_AXBURST_ENCODING::FIXED,
arcache: axi_pkg::AXI_ARCACHE_ENCODING::DEV_NO_BUF,
arprot: uN[3]:0,
arqos: uN[4]:0
};
let (tok, ar_payload, ar_valid) = recv_non_blocking(tok, ar_ch, zero_axi_ar_t);
let r_addr = if ar_valid { ar_payload.araddr } else { state.raddr };

// Handle Read from CSR
let tok = send_if(tok, read_req, ar_valid, csr::ReadWordReq(r_addr));
let (tok, r_data, csr_read_valid) = recv_non_blocking(tok, read_resp, zero!<csr::ReadResp>());
let (tok, r_data, csr_read_valid) =
recv_non_blocking(tok, read_resp, zero!<csr::ReadResp>());

// R Channel Handler
let tok = send_if(tok, r_ch, csr_read_valid, axi_r_t{
rid: uN[ID_W]: 0,
rdata: r_data.data,
rresp: axi_pkg::AXI_READ_RESPONSE_CODES::OKAY,
rlast: uN[1]:1
});

axi_csr_state {
waddr: w_addr,
wdata: w_data,
raddr: r_addr,
rdata: r_data.data
}
let tok = send_if(
tok, r_ch, csr_read_valid,
axi_r_t {
rid: uN[ID_W]:0,
rdata: r_data.data,
rresp: axi_pkg::AXI_READ_RESPONSE_CODES::OKAY,
rlast: uN[1]:1
});

axi_csr_state { waddr: w_addr, wdata: w_data, raddr: r_addr, rdata: r_data.data }
}
}

// Helper functions
pub fn prep_axi_w <ADDR_W:u32,DATA_W:u32, ID_W: u32, STRB_W: u32>(
addr: uN[ADDR_W],
data: uN[DATA_W],
id: uN[ID_W],
strb: uN[STRB_W]) -> (axi_aw_t,axi_w_t){
pub fn prep_axi_w<ADDR_W: u32, DATA_W: u32, ID_W: u32, STRB_W: u32>
(addr: uN[ADDR_W], data: uN[DATA_W], id: uN[ID_W], strb: uN[STRB_W]) -> (axi_aw_t, axi_w_t) {
let aw = axi_aw_t {
awid: id,
awaddr: addr,
awsize: axi_pkg::AXI_AXSIZE_ENCODING::MAX_8B_TRANSFER,
awprot: u3:0
};
let w = axi_w_t {
wdata: data,
wstrb: strb,
wlast: u1:1
awid: id, awaddr: addr, awsize: axi_pkg::AXI_AXSIZE_ENCODING::MAX_8B_TRANSFER, awprot: u3:0
};
let w = axi_w_t { wdata: data, wstrb: strb, wlast: u1:1 };
(aw, w)
}

pub fn prep_axi_r <ADDR_W:u32,ID_W: u32>(
addr: uN[ADDR_W],
id: uN[ID_W],
) -> axi_ar_t {
pub fn prep_axi_r<ADDR_W: u32, ID_W: u32>(addr: uN[ADDR_W], id: uN[ID_W]) -> axi_ar_t {
let ar = axi_ar_t {
arid: id,
araddr: addr,
arregion: uN[4]:0,
arlen: uN[8]:1,
arsize: axi_pkg::AXI_AXSIZE_ENCODING::MAX_1B_TRANSFER,
arburst: axi_pkg::AXI_AXBURST_ENCODING::FIXED,
arcache: axi_pkg::AXI_ARCACHE_ENCODING::DEV_NO_BUF,
arprot: uN[3]:0,
arqos: uN[4]:0
arid: id,
araddr: addr,
arregion: uN[4]:0,
arlen: uN[8]:1,
arsize: axi_pkg::AXI_AXSIZE_ENCODING::MAX_1B_TRANSFER,
arburst: axi_pkg::AXI_AXBURST_ENCODING::FIXED,
arcache: axi_pkg::AXI_ARCACHE_ENCODING::DEV_NO_BUF,
arprot: uN[3]:0,
arqos: uN[4]:0
};

(ar)
Expand All @@ -223,8 +193,7 @@ proc test_axi_csr {
b_ch: chan<axi_b_t<TEST_0_ID_W>> in;
ar_ch: chan<axi_ar_t<TEST_0_ID_W, TEST_0_ADDR_W>> out;
r_ch: chan<axi_r_t<TEST_0_ID_W, TEST_0_DATA_W>> in;

all_csr: chan<csr::AllCSR<TEST_0_DATA_W,TEST_0_REGS_N>> in;
all_csr: chan<csr::AllCSR<TEST_0_DATA_W, TEST_0_REGS_N>> in;
terminator: chan<bool> out;

config(terminator: chan<bool> out) {
Expand All @@ -233,15 +202,16 @@ proc test_axi_csr {
let (b_req_s, b_req_r) = chan<axi_b_t<TEST_0_ID_W>>;
let (ar_ch_s, ar_ch_r) = chan<axi_ar_t<TEST_0_ID_W, TEST_0_ADDR_W>>;
let (r_ch_s, r_ch_r) = chan<axi_r_t<TEST_0_ID_W, TEST_0_DATA_W>>;
let (all_csr_s, all_csr_r) = chan<csr::AllCSR<TEST_0_DATA_W,TEST_0_REGS_N>>;
let (all_csr_s, all_csr_r) = chan<csr::AllCSR<TEST_0_DATA_W, TEST_0_REGS_N>>;

spawn axi_csr<TEST_0_ID_W, TEST_0_ADDR_W, TEST_0_DATA_W, TEST_0_STRB_W, TEST_0_REGS_N>(
aw_req_r, w_req_r, b_req_s, ar_ch_r, r_ch_s, all_csr_s);
aw_req_r, w_req_r, b_req_s, ar_ch_r, r_ch_s, all_csr_s);
(aw_req_s, w_req_s, b_req_r, ar_ch_s, r_ch_r, all_csr_r, terminator)
}

init { () }
next(tok: token, state:()) {

next(tok: token, state: ()) {
let id = uN[TEST_0_ID_W]:0;
let strb = std::unsigned_max_value<TEST_0_STRB_W>();

Expand All @@ -263,7 +233,7 @@ proc test_axi_csr {
let ar = prep_axi_r(addr, id);
let tok = send(tok, ar_ch, ar);
let (tok, rcv) = recv(tok, r_ch);
assert_eq(rcv.rdata,(u32:0xFFFFFFFF + i) as uN[TEST_0_DATA_W] );
assert_eq(rcv.rdata, (u32:0xFFFFFFFF + i) as uN[TEST_0_DATA_W]);
(tok)
}(tok);

Expand All @@ -279,17 +249,19 @@ const SYNTH_0_REGS_N = u32:14;

// Verilog example
proc axi_csr_8_32_14 {
config(
aw_ch: chan<axi_aw_t<SYNTH_0_ID_W, SYNTH_0_ADDR_W>> in,
w_ch: chan<axi_w_t<SYNTH_0_DATA_W, SYNTH_0_STRB_W>> in,
b_ch: chan<axi_b_t<SYNTH_0_ID_W>> out,
ar_ch: chan<axi_ar_t<SYNTH_0_ID_W, SYNTH_0_ADDR_W >> in,
r_ch: chan<axi_r_t<SYNTH_0_ID_W, SYNTH_0_DATA_W>> out,
all_csr: chan<csr::AllCSR<SYNTH_0_DATA_W,SYNTH_0_REGS_N>> out
) {spawn axi_csr<SYNTH_0_ID_W, SYNTH_0_ADDR_W, SYNTH_0_DATA_W, SYNTH_0_STRB_W, SYNTH_0_REGS_N>(aw_ch,w_ch,b_ch,ar_ch,
r_ch,all_csr);
()}
config(aw_ch: chan<axi_aw_t<SYNTH_0_ID_W, SYNTH_0_ADDR_W>> in, w_ch
:
chan<axi_w_t<SYNTH_0_DATA_W, SYNTH_0_STRB_W>> in,
b_ch: chan<axi_b_t<SYNTH_0_ID_W>> out, ar_ch: chan<axi_ar_t<SYNTH_0_ID_W, SYNTH_0_ADDR_W>> in, r_ch
:
chan<axi_r_t<SYNTH_0_ID_W, SYNTH_0_DATA_W>> out,
all_csr: chan<csr::AllCSR<SYNTH_0_DATA_W, SYNTH_0_REGS_N>> out) {
spawn axi_csr<SYNTH_0_ID_W, SYNTH_0_ADDR_W, SYNTH_0_DATA_W, SYNTH_0_STRB_W, SYNTH_0_REGS_N>(
aw_ch, w_ch, b_ch, ar_ch, r_ch, all_csr);
()
}

init { () }
next(tok: token, state: ()) {}

next(tok: token, state: ()) { }
}
2 changes: 1 addition & 1 deletion xls/modules/axi4/dma/config.x
View file
Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ fn test_axi_config() {
// CSR Config
pub const CSR_DATA_W = AXI_0_DATA_W;
pub const CSR_ADDR_W = AXI_0_ADDR_W;
pub const CSR_REGS_N = u32:14; //std::upow(u32:2, CSR_ADDR_W);
pub const CSR_REGS_N = u32:14; //std::upow(u32:2, CSR_ADDR_W);

// Register Map
pub const CONTROL_REGISTER = uN[CSR_ADDR_W]:0x00;
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