Update talks CSV (#151)

* Update talks CSV * Update talks CSV
fossi-foundation · Sep 13, 2024 · a1d47da · a1d47da
1 parent f3ad8bf
commit a1d47da
Showing 1 changed file with 12 additions and 11 deletions.
diff --git a/content/orconf/2024/talks.csv b/content/orconf/2024/talks.csv
@@ -6,25 +6,26 @@ Fri,11:00,Normal,The Saturn Vector Unit: Design of a Fully Compliant Open-Source
 Fri,11:20,Normal,VexiiRiscv : A Debian demonstration,Charles Papon,Core,"[The VexiiRiscv (Vex2Risc5) project](https://github.com/SpinalHDL/VexiiRiscv) aim at replacing VexRiscv and extends its scope with features such as multi-issue, hardware prefetcher, 64 bits support, ... This presentation will mainly be a live demonstration of the project running Debian on FPGA, exposing the level of performance achievable on such system including boot, userland, some demos and finaly a few slides."
 Fri,11:40,Normal,FazyRV: A RISC-V Core that Scales to Your Needs,Meinhard Kissich,Core,"[FazyRV](https://github.com/meiniKi/FazyRV) is a scalable RISC-V core that can be synthesized into a (1-)bit-serial, 2-, 4-, or 8-bit-serial implementation to fulfill your performance requirements with the least area (resp. resources) demand. FazyRV provides manifold variants to adapt to the target technology by, e.g., avoiding dual-port BRAM at the cost of an additional clock cycle. Contradictory to hand-optimized cores at the gate level, FazyRV tries to avoid manual low-level optimizations to increase readability and simplify adaptations. This talk gives an insight into the open-source FazyRV core and its design objectives. We show how the area demand scales, answer why there is no 16-bit variant, discuss how the performance can be improved, and outline possible extensions to improve the current FazyRV design."
 Fri,12:00,Normal,A very small cross compiler for OpenRISC and maybe your homebrew processor,Jörg Mische,Tool,"[PunyCC](https://github.com/bobbl/punycc) is a cross compiler for a very small subset of C. Only one source file, no preprocessor, no structs, no floating point and only one datatype that can be used as unsigend int or pointer to char. Due to these simplifications the compiler source code is very small and can easily be adopted to a new target instruction set. So far PunyCC supported 4 architectures: ARM Thumb-2, RISC-V, x86-32 and WebAssembly. It can compile itself and thus provides cross compilers from any of the instruction sets to any other. This talk presents how easy it is to add OpenRISC support to PunyCC. Use it as a blueprint for porting PunyCC to your own special instruction set."
-Fri,12:20,Break,Lunch Break,,,
-Fri,13:00,Normal,Roadmap for Open Source EDA in Europe,Stefan Wallentowitz,Advocacy,"Open source silicon and open source EDA tools have been identified as strategically important for European sovereignty. The [GoIT!](https://wiki.goit-project.eu/index.php?title=Main_Page) project and FOSSi Foundation have been tasked with creating a roadmap and recommendations for open source EDA in Europe. In this presentation, we will give an overview about the roadmap and initiate the community feedback period, which is extremely important for the success of the roadmap."
-Fri,13:30,Normal,"New open source IP, tools and verification flows for Caliptra 2.0",Karol Gugala,"IP, Verification","CHIPS Alliance’s open source [Caliptra Root of Trust Project](https://github.com/chipsalliance/Caliptra) (a collaboration between AMD, Google, Microsoft and NVIDIA) is heading towards a 2.0 release. This talk will cover recent open source developments resulting from [Antmicro’s](https://antmicro.com/) involvement in the project, expanding on last year’s update at ORConf: a new open source I3C core built for use in future Caliptra integrations, further developments in the [RISC-V-based VeeR](https://github.com/chipsalliance/Cores-VeeR-EH1) core including PMP, ePMP and User Mode support, fully open verification of the AXI bus interface with Verilator and axi-vip verification IP and a number of improvements related to coverage visualization, automated documentation and chip aggregation. The talk will also present the SystemRDL integration with Renode speeding up generation of the co-simulation verification environment, as well as Caliptra’s entry in Antmicro’s System Designer which lets you explore the SoC’s structure, RTL and verification artifacts from a block diagram perspective."
-Fri,13:50,Normal,The future of FuseSoC,Olof Kindgren,Tool,"While individual projects like Linux and GCC paved the road for open source software success, it can be argued that the thing that really enabled scaling up development of Linux-based solutions was the idea of package management. Having a common way to install software and describe their relations made it possible to rapidly create custom systems. The same can be said for language-specific package managers like pip for Python or Cargo for Rust.
+Fri,12:30,Break,Lunch Break,,,
+Fri,13:30,Normal,Roadmap for Open Source EDA in Europe,Stefan Wallentowitz,Advocacy,"Open source silicon and open source EDA tools have been identified as strategically important for European sovereignty. The [GoIT!](https://wiki.goit-project.eu/index.php?title=Main_Page) project and FOSSi Foundation have been tasked with creating a roadmap and recommendations for open source EDA in Europe. In this presentation, we will give an overview about the roadmap and initiate the community feedback period, which is extremely important for the success of the roadmap."
+Fri,14:00,Normal,"New open source IP, tools and verification flows for Caliptra 2.0",Karol Gugala,"IP, Verification","CHIPS Alliance’s open source [Caliptra Root of Trust Project](https://github.com/chipsalliance/Caliptra) (a collaboration between AMD, Google, Microsoft and NVIDIA) is heading towards a 2.0 release. This talk will cover recent open source developments resulting from [Antmicro’s](https://antmicro.com/) involvement in the project, expanding on last year’s update at ORConf: a new open source I3C core built for use in future Caliptra integrations, further developments in the [RISC-V-based VeeR](https://github.com/chipsalliance/Cores-VeeR-EH1) core including PMP, ePMP and User Mode support, fully open verification of the AXI bus interface with Verilator and axi-vip verification IP and a number of improvements related to coverage visualization, automated documentation and chip aggregation. The talk will also present the SystemRDL integration with Renode speeding up generation of the co-simulation verification environment, as well as Caliptra’s entry in Antmicro’s System Designer which lets you explore the SoC’s structure, RTL and verification artifacts from a block diagram perspective."
+Fri,14:20,Normal,The future of FuseSoC,Olof Kindgren,Tool,"While individual projects like Linux and GCC paved the road for open source software success, it can be argued that the thing that really enabled scaling up development of Linux-based solutions was the idea of package management. Having a common way to install software and describe their relations made it possible to rapidly create custom systems. The same can be said for language-specific package managers like pip for Python or Cargo for Rust.
 
 On the chip design side, [FuseSoC](https://fusesoc.net/) has been doing the same thing since its inception 2011. It is by now likely the world's most widely used package manager, both for open source projects and for proprietary code.
 
 The background of FuseSoC has been presented several times over the years, so this presentation aims to instead look ahead and see what new features that are in store for FuseSoC and its sister project Edalize."
-Fri,14:10,Normal,Surfer - An Extensible and Snappy Waveform Viewer,Frans Skarman,Tool,"[Surfer](https://surfer-project.org/) is a new waveform viewer focused on extensibility and a snappy interface. This presentation will briefly show off Surfer, showcase off how an extensible waveform viewer can be used for more effective debugging such as translating types from high level HDLs, visualising the results of waveform analysis, or even as a teaching tool. The presentation will also showcase some recently added features such as transaction visualization, the ""Surver"" headless interface, and scriptable plugins."
-Fri,14:30,Break,Coffee Break,,,
-Fri,15:00,Normal,APyTypes - NumPy for people that care about their bits,Oscar Gustafsson,Tool,"[APyTypes](https://github.com/apytypes/apytypes) is an array library for Python with highly configurable bit-accurate fixed-point and floating-point data types of arbitrary word length written in C++. Hence, it can be used to easily simulate finite word length effects and to provide reference data for hardware implementations. This talk discuss features of APyTypes, how to work with it, and how it compares against other libraries with a similar purpose."
-Fri,15:20,Normal,Development of Certificate Courses and Status Quo of Digital EDA Course using IHP-SG13G2,Christian Wittke,"Education, PDK","This talk will present the ongoing effort and progress in creating the OS-EDA course. An overview of the available materials, lectures, and hands-on components will be included. Additionally, we will explain how to participate and use the materials independently. A first test run of the course, planned to be held in-house at IHP, will be announced during this talk at ORConf. The course's overall goal is to help participants understand and use open-source EDA tools to create an open-source tapeout, with IHP as the default target chip factory and the usage of OPENROAD. The course will be available in English, with all materials hosted in a public Git repository under an open-source license. This work is funded by the German Federal Ministry of Education and Research in the Project FMD-QNC (16ME0831).This talk will present the development of certificate courses within the FMD-QNC project, which will be part of an educational platform aimed at training individuals from trainees to academics. The OS-EDA courses under development at IHP target academics and career changers. We will present the progress in creating the digital OS-EDA course, including an overview of the available materials, lectures, and hands-on components. Additionally, we will explain how to participate and use the materials independently.
+Fri,14:40,Normal,Surfer - An Extensible and Snappy Waveform Viewer,Frans Skarman,Tool,"[Surfer](https://surfer-project.org/) is a new waveform viewer focused on extensibility and a snappy interface. This presentation will briefly show off Surfer, showcase off how an extensible waveform viewer can be used for more effective debugging such as translating types from high level HDLs, visualising the results of waveform analysis, or even as a teaching tool. The presentation will also showcase some recently added features such as transaction visualization, the ""Surver"" headless interface, and scriptable plugins."
+Fri,15:00,Break,Coffee Break,,,
+Fri,15:40,Normal,APyTypes - NumPy for people that care about their bits,Oscar Gustafsson,Tool,"[APyTypes](https://github.com/apytypes/apytypes) is an array library for Python with highly configurable bit-accurate fixed-point and floating-point data types of arbitrary word length written in C++. Hence, it can be used to easily simulate finite word length effects and to provide reference data for hardware implementations. This talk discuss features of APyTypes, how to work with it, and how it compares against other libraries with a similar purpose."
+Fri,16:10,Normal,Development of Certificate Courses and Status Quo of Digital EDA Course using IHP-SG13G2,Christian Wittke,"Education, PDK","This talk will present the ongoing effort and progress in creating the OS-EDA course. An overview of the available materials, lectures, and hands-on components will be included. Additionally, we will explain how to participate and use the materials independently. A first test run of the course, planned to be held in-house at IHP, will be announced during this talk at ORConf. The course's overall goal is to help participants understand and use open-source EDA tools to create an open-source tapeout, with IHP as the default target chip factory and the usage of OPENROAD. The course will be available in English, with all materials hosted in a public Git repository under an open-source license. This work is funded by the German Federal Ministry of Education and Research in the Project FMD-QNC (16ME0831).This talk will present the development of certificate courses within the FMD-QNC project, which will be part of an educational platform aimed at training individuals from trainees to academics. The OS-EDA courses under development at IHP target academics and career changers. We will present the progress in creating the digital OS-EDA course, including an overview of the available materials, lectures, and hands-on components. Additionally, we will explain how to participate and use the materials independently.
 
 A first test run of the course, planned to be held in-house at IHP, will be announced during this talk at ORConf. The overall goal of the course is to help participants understand and use open-source EDA tools to create an open-source tapeout, with IHP as the default target chip factory and the use of OPENROAD.
 
 The course will be available in English, with all materials hosted in a public Git repository under an open-source license. This work is funded by the German Federal Ministry of Education and Research as part of the FMD-QNC project (16ME0831)."
-Fri,15:40,Normal,"Making sound & graphics ASIC: ""Drop"" audio-visual demo chip on 130nm",Renaldas Zioma,Design,"Design and development process of the ""Drop"" demo for the [TinyTapeout Demoscene 2024 competition](https://tinytapeout.com/competitions/demoscene/). The dedicated ASIC is a self contained 150x220 um piece of silicon built on a 130 nm process, requires no CPU, GPU or external memory and produces VGA signal in a ""racing the beam"" fashion. The talk will cover tools and hardware used during the development of the demo. Optimisation techniques to fit multiple graphical effects into extremely tight area of 150x220 um and quick comparison of the dedicated ASIC design vs ""classical"" chips for graphics and audio synthesis."
-Fri,16:00,Normal,My open source analog microelectronics journey,Matt Venn,"Analog, Design","Analog microelectronics is a crucial but often overlooked part of ASIC design. In this talk I will share my experience getting started with analog microelectronics, and taping out my first few designs. I will cover motivation, tools, my designs, and my success and failures so far. The presentation will end with a discussion on how this fascinating topic fits into the wider picture of open source silicon and the next steps needed to enable radio transmitters and receivers."
-Fri,16:20,Normal,,,,
+Fri,16:30,Normal,"Making sound & graphics ASIC: ""Drop"" audio-visual demo chip on 130nm",Renaldas Zioma,Design,"Design and development process of the ""Drop"" demo for the [TinyTapeout Demoscene 2024 competition](https://tinytapeout.com/competitions/demoscene/). The dedicated ASIC is a self contained 150x220 um piece of silicon built on a 130 nm process, requires no CPU, GPU or external memory and produces VGA signal in a ""racing the beam"" fashion. The talk will cover tools and hardware used during the development of the demo. Optimisation techniques to fit multiple graphical effects into extremely tight area of 150x220 um and quick comparison of the dedicated ASIC design vs ""classical"" chips for graphics and audio synthesis."
+Fri,16:50,Normal,My open source analog microelectronics journey,Matt Venn,"Analog, Design","Analog microelectronics is a crucial but often overlooked part of ASIC design. In this talk I will share my experience getting started with analog microelectronics, and taping out my first few designs. I will cover motivation, tools, my designs, and my success and failures so far. The presentation will end with a discussion on how this fascinating topic fits into the wider picture of open source silicon and the next steps needed to enable radio transmitters and receivers."
+Fri,17:30,Break,Drinks & snacks at confrence venue,,,
+Fri,19:30,Break,Saturday End,,,
 Sat,09:00,Normal,Open Source Standard Cell Library Design,Antoine Sirianni,PDK,"With the avenue of AI as a game changer, what would Open Source Standard Cell Library Design consist in to date? Where to start ? Let's focus on combinatorics to provide with an unexpected contribution."
 Sat,09:20,Normal,Project Arrakeen: One API to rule all PDKs,Staf Verhaegen,PDK,"[Project Arrakeen](https://gitlab.com/Chips4Makers/c4m-arrakeen) is an umbrella project for providing a python framework for portable and scalable digital and analog circuits. It is based on the PDKMaster base project which provide a uniform API to PDK data and generation of circuit and layouts. On this base project other projects are being built that provide standard cells, IO cells, SRAM compiler and analog blocks. In this talk the state of the Arrakeen project and it's subprojects for the three supported open source PDKs, e.g. Sky130, IHP SG13G2 and GF180MCU will be presented."
 Sat,09:40,Normal,Porting of Proprietary PDK to Digital Open-Source EDA Tools,Tomasz Hemperek,PDK,"Open-source tools for ASIC design are gaining momentum due to their cost-effectiveness, customizability, and reliability. These tools have proven their value through multiple successful designs in recent years. This talk will present our experience in successfully porting a proprietary 110nm Process Design Kit (PDK) to open-source EDA tools such as Yosys and OpenRoad. We will discuss both the successes and challenges encountered during this process, using the prototype Gbit serial data link as a case study."