Digital Logic 2023, Course Final Project
This project is the final test of the "Digital Logic" course at the Polytechnic of Milan, A.Y. 2022/23. I did this project in pairs collaborating with my university mate Samuele Galli.
Evaluation: 30 / 30
Project: FILE
Description of the problem: ITA , ENG
The objective of the project is to realize a HW component that, having received as input a memory address and information regarding the required output channel, prints the contents of the address on the specified channel.
Seven interfaces are presented, including 2 primary inputs (W and START), both 1 bit, and 5 outputs (Z0, Z1, Z2, Z3, DONE), of which, the first 4 (8 bits), on which all bits of the memory word are to be reported, and DONE 1 bit. There is also a reset signal (RESET) and a clock signal (CLK), unique to the component.
The specification calls for implementing a hardware module in VHDL that interfaces with a memory and receives information via a one-bit serial input about a memory location whose contents are to be routed to one of four available output channels.
| test | description |
|---|---|
| 0bit | corner case with length of address 0 |
| 16bit | corner case with length of address 0 |
| data | generic test |
| reset | reset during processing |
| long | stress test |
- Xilinx Vivado