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initial attempt at support for loongarch
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(WIP)

Change-Id: I0ac1aef31a0ea6b2f45abca2417b834b3182affd
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cooljeanius committed Oct 19, 2024
1 parent e4cd87b commit 4454968
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8 changes: 8 additions & 0 deletions src/bfd/Makefile.am
Original file line number Diff line number Diff line change
Expand Up @@ -1272,6 +1272,14 @@ elf64-ia64.c : elfxx-ia64.c
$(SED) -e s/NN/64/g < $(srcdir)/elfxx-ia64.c >> elf64-ia64.new
mv -f $(AM_V_v) elf64-ia64.new $@

elf32-loongarch.c : elfnn-loongarch.c
$(AM_V_at)echo "#line 1 \"$<\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/32/g < $< >> $@

elf64-loongarch.c : elfnn-loongarch.c
$(AM_V_at)echo "#line 1 \"$<\"" > $@
$(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@

peigen.c : peXXigen.c
$(AM_V_at)rm -f $(AM_V_v) $@
echo "/* DO NOT EDIT! -*- buffer-read-only: t -*- */" > peigen.new
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8 changes: 8 additions & 0 deletions src/bfd/Makefile.in

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40 changes: 40 additions & 0 deletions src/bfd/archures.c
Original file line number Diff line number Diff line change
Expand Up @@ -139,6 +139,8 @@ DESCRIPTION
.#define bfd_mach_spu 256
. bfd_arch_mips, {* MIPS Rxxxx *}
.#define bfd_mach_mips3000 3000
.#define bfd_mach_mips_loongson_2e 3001
.#define bfd_mach_mips_loongson_2f 3002
.#define bfd_mach_mips3900 3900
.#define bfd_mach_mips4000 4000
.#define bfd_mach_mips4010 4010
Expand Down Expand Up @@ -458,6 +460,42 @@ DESCRIPTION
.#define bfd_mach_nios2r2 2
. bfd_arch_visium, {* Visium *}
.#define bfd_mach_visium 1
. bfd_arch_wasm32, {* WebAssembly. *}
.#define bfd_mach_wasm32 1
. bfd_arch_pru, {* PRU. *}
.#define bfd_mach_pru 0
. bfd_arch_nfp, {* Netronome Flow Processor *}
.#define bfd_mach_nfp3200 0x3200
.#define bfd_mach_nfp6000 0x6000
. bfd_arch_csky, {* C-SKY. *}
.#define bfd_mach_ck_unknown 0
.#define bfd_mach_ck510 1
.#define bfd_mach_ck610 2
.#define bfd_mach_ck801 3
.#define bfd_mach_ck802 4
.#define bfd_mach_ck803 5
.#define bfd_mach_ck807 6
.#define bfd_mach_ck810 7
.#define bfd_mach_ck860 8
. bfd_arch_loongarch, {* LoongArch *}
.#define bfd_mach_loongarch32 1
.#define bfd_mach_loongarch64 2
. bfd_arch_amdgcn, {* AMDGCN *}
.#define bfd_mach_amdgcn_unknown 0x000
.#define bfd_mach_amdgcn_gfx900 0x02c
.#define bfd_mach_amdgcn_gfx904 0x02e
.#define bfd_mach_amdgcn_gfx906 0x02f
.#define bfd_mach_amdgcn_gfx908 0x030
.#define bfd_mach_amdgcn_gfx90a 0x03f
.#define bfd_mach_amdgcn_gfx1010 0x033
.#define bfd_mach_amdgcn_gfx1011 0x034
.#define bfd_mach_amdgcn_gfx1012 0x035
.#define bfd_mach_amdgcn_gfx1030 0x036
.#define bfd_mach_amdgcn_gfx1031 0x037
.#define bfd_mach_amdgcn_gfx1032 0x038
.#define bfd_mach_amdgcn_gfx1100 0x041
.#define bfd_mach_amdgcn_gfx1101 0x046
.#define bfd_mach_amdgcn_gfx1102 0x047
. bfd_arch_last
. };
*/
Expand Down Expand Up @@ -532,6 +570,7 @@ extern const bfd_arch_info_type bfd_iq2000_arch;
extern const bfd_arch_info_type bfd_k1om_arch;
extern const bfd_arch_info_type bfd_l1om_arch;
extern const bfd_arch_info_type bfd_lm32_arch;
extern const bfd_arch_info_type bfd_loongarch_arch;
extern const bfd_arch_info_type bfd_m32c_arch;
extern const bfd_arch_info_type bfd_m32r_arch;
extern const bfd_arch_info_type bfd_m68hc11_arch;
Expand Down Expand Up @@ -626,6 +665,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_k1om_arch,
&bfd_l1om_arch,
&bfd_lm32_arch,
&bfd_loongarch_arch,
&bfd_m32c_arch,
&bfd_m32r_arch,
&bfd_m68hc11_arch,
Expand Down
1 change: 1 addition & 0 deletions src/bfd/bfd-in.h
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@ extern "C" {

#include "ansidecl.h"
#include "symcat.h"
#include <stdbool.h>
#if defined(__STDC__) || defined(ALMOST_STDC) || defined(HAVE_STRINGIZE)
# ifndef SABER
/* This hack is to avoid a problem with some strict ANSI C preprocessors.
Expand Down
39 changes: 39 additions & 0 deletions src/bfd/bfd-in2.h
Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@ extern "C" {

#include "ansidecl.h"
#include "symcat.h"
#include <stdbool.h>
#if defined(__STDC__) || defined(ALMOST_STDC) || defined(HAVE_STRINGIZE)
# ifndef SABER
/* This hack is to avoid a problem with some strict ANSI C preprocessors.
Expand Down Expand Up @@ -1902,6 +1903,8 @@ enum bfd_architecture
#define bfd_mach_spu 256
bfd_arch_mips, /* MIPS Rxxxx */
#define bfd_mach_mips3000 3000
#define bfd_mach_mips_loongson_2e 3001
#define bfd_mach_mips_loongson_2f 3002
#define bfd_mach_mips3900 3900
#define bfd_mach_mips4000 4000
#define bfd_mach_mips4010 4010
Expand Down Expand Up @@ -2221,6 +2224,42 @@ enum bfd_architecture
#define bfd_mach_nios2r2 2
bfd_arch_visium, /* Visium */
#define bfd_mach_visium 1
bfd_arch_wasm32, /* WebAssembly. */
#define bfd_mach_wasm32 1
bfd_arch_pru, /* PRU. */
#define bfd_mach_pru 0
bfd_arch_nfp, /* Netronome Flow Processor */
#define bfd_mach_nfp3200 0x3200
#define bfd_mach_nfp6000 0x6000
bfd_arch_csky, /* C-SKY. */
#define bfd_mach_ck_unknown 0
#define bfd_mach_ck510 1
#define bfd_mach_ck610 2
#define bfd_mach_ck801 3
#define bfd_mach_ck802 4
#define bfd_mach_ck803 5
#define bfd_mach_ck807 6
#define bfd_mach_ck810 7
#define bfd_mach_ck860 8
bfd_arch_loongarch, /* LoongArch */
#define bfd_mach_loongarch32 1
#define bfd_mach_loongarch64 2
bfd_arch_amdgcn, /* AMDGCN */
#define bfd_mach_amdgcn_unknown 0x000
#define bfd_mach_amdgcn_gfx900 0x02c
#define bfd_mach_amdgcn_gfx904 0x02e
#define bfd_mach_amdgcn_gfx906 0x02f
#define bfd_mach_amdgcn_gfx908 0x030
#define bfd_mach_amdgcn_gfx90a 0x03f
#define bfd_mach_amdgcn_gfx1010 0x033
#define bfd_mach_amdgcn_gfx1011 0x034
#define bfd_mach_amdgcn_gfx1012 0x035
#define bfd_mach_amdgcn_gfx1030 0x036
#define bfd_mach_amdgcn_gfx1031 0x037
#define bfd_mach_amdgcn_gfx1032 0x038
#define bfd_mach_amdgcn_gfx1100 0x041
#define bfd_mach_amdgcn_gfx1101 0x046
#define bfd_mach_amdgcn_gfx1102 0x047
bfd_arch_last
};

Expand Down
45 changes: 44 additions & 1 deletion src/bfd/config.bfd
Original file line number Diff line number Diff line change
Expand Up @@ -107,20 +107,26 @@ case "${targ_cpu}" in
aarch64*) targ_archs="bfd_aarch64_arch bfd_arm_arch";;
alpha*) targ_archs=bfd_alpha_arch ;;
am34*|am33_2.0*) targ_archs=bfd_mn10300_arch ;;
arc*) targ_archs=bfd_arc_arch ;;
arm*) targ_archs=bfd_arm_arch ;;
amdgcn*) targ_archs=bfd_amdgcn_arch ;;
bfin*) targ_archs=bfd_bfin_arch ;;
c30*) targ_archs=bfd_tic30_arch ;;
c4x*) targ_archs=bfd_tic4x_arch ;;
c54x*) targ_archs=bfd_tic54x_arch ;;
cr16*) targ_archs=bfd_cr16_arch ;;
crisv32) targ_archs=bfd_cris_arch ;;
crx*) targ_archs=bfd_crx_arch ;;
csky*) targ_archs=bfd_csky_arch ;;
dlx*) targ_archs=bfd_dlx_arch ;;
fido*) targ_archs=bfd_m68k_arch ;;
hppa*) targ_archs=bfd_hppa_arch ;;
i[3-7]86) targ_archs=bfd_i386_arch ;;
i370) targ_archs=bfd_i370_arch ;;
ia16) targ_archs=bfd_i386_arch ;;
kvx) targ_archs=bfd_kvx_arch ;;
lm32) targ_archs=bfd_lm32_arch ;;
loongarch*) targ_archs=bfd_loongarch_arch ;;
m6811*|m68hc11*) targ_archs="bfd_m68hc11_arch bfd_m68hc12_arch bfd_m9s12x_arch bfd_m9s12xg_arch" ;;
m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch bfd_m9s12x_arch bfd_m9s12xg_arch" ;;
m68*) targ_archs=bfd_m68k_arch ;;
Expand All @@ -135,7 +141,10 @@ or32*) targ_archs=bfd_or32_arch ;;
pdp11*) targ_archs=bfd_pdp11_arch ;;
pj*) targ_archs="bfd_pj_arch bfd_i386_arch";;
powerpc*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
pru*) targ_archs=bfd_pru_arch ;;
riscv*) targ_archs=bfd_riscv_arch ;;
rs6000) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
s12z*) targ_archs=bfd_s12z_arch ;;
s390*) targ_archs=bfd_s390_arch ;;
sh*) targ_archs=bfd_sh_arch ;;
sparc*) targ_archs=bfd_sparc_arch ;;
Expand All @@ -145,11 +154,12 @@ tilegx*) targ_archs=bfd_tilegx_arch ;;
tilepro*) targ_archs=bfd_tilepro_arch ;;
thumb*) targ_archs=bfd_arm_arch ;;
v850*) targ_archs="bfd_v850_arch bfd_v850_rh850_arch" ;;
visium*) targ_archs=bfd_visium_arch ;;
x86_64*) targ_archs=bfd_i386_arch ;;
xscale*) targ_archs=bfd_arm_arch ;;
xtensa*) targ_archs=bfd_xtensa_arch ;;
xgate) targ_archs=bfd_xgate_arch ;;
z80|r800) targ_archs=bfd_z80_arch ;;
z80*|r800|z180|gbz80|ez80*) targ_archs=bfd_z80_arch ;;
z8k*) targ_archs=bfd_z8k_arch ;;
am33_2.0) targ_archs=bfd_mn10300_arch ;;
*) targ_archs=bfd_${targ_cpu}_arch ;;
Expand Down Expand Up @@ -1909,6 +1919,20 @@ case "${targ}" in
targ_underscore=yes
;;

#ifdef BFD64
loongarch32-*)
targ_defvec=loongarch_elf32_vec
targ_selvecs="loongarch_elf32_vec"
want64=true
;;

loongarch64-*)
targ_defvec=loongarch_elf64_vec
targ_selvecs="loongarch_elf32_vec loongarch_elf64_vec loongarch64_pei_vec"
want64=true
;;
#endif

*-*-ieee*)
targ_defvec=ieee_vec
;;
Expand All @@ -1928,6 +1952,12 @@ case "${targ}" in
targ_selvecs=ieee_vec
;;
# END OF targmatch.h
bpf-*-*)
echo "*** Configuration $targ is not fully supported." >&2
echo "*** Use bpf or bpf-*-none as the target instead." >&2
exit 1
;;

*)
echo 1>&2 "*** BFD does not support target ${targ}."
echo 1>&2 "*** Look in bfd/config.bfd for supported targets."
Expand Down Expand Up @@ -1984,3 +2014,16 @@ case "${targ_defvec} ${targ_selvecs}" in
targ_archs="${targ_archs} bfd_k1om_arch"
;;
esac

# If we support Intel MCU target, then add support for bfd_iamcu_arch.
case "${targ_defvec} ${targ_selvecs}" in
*iamcu_elf32*)
targ_archs="$targ_archs bfd_iamcu_arch"
;;
esac

case "${targ}" in
mipsisa32r6* | mipsisa64r6* | mips*-img-*)
targ_cflags="$targ_cflags -DMIPS_DEFAULT_R6=1"
;;
esac
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