GitHub - bjybs123/Single-Cycle-RV32I: Verilog Implementation of RISC-V RV32I Instruction Set Architecture

bjybs123 / Single-Cycle-RV32I Public

Verilog Implementation of RISC-V RV32I Instruction Set Architecture

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
ALU.v		ALU.v
ALUControl.v		ALUControl.v
Adder.v		Adder.v
ControlUnit.v		ControlUnit.v
DataMem.v		DataMem.v
ImmediateGen.v		ImmediateGen.v
InstrMem.v		InstrMem.v
MUX.v		MUX.v
PC.v		PC.v
RV32I.v		RV32I.v
RegisterFile.v		RegisterFile.v
Widthcntl.v		Widthcntl.v