Upgraded folding and CP layers

[loreloc]

New features

1. Tensorized circuits constructed from region graphs with heterogeneous partition node arities can now be folded. For example, we are able to fold CP layers with product units having a different number of inputs.
2. Masking the gradients of parameters has been tested with this unit test.
3. All CP-derived layers have been generalized to support any arity.

Notes

1. The re-parametrization must be aware if a layer is folded and if padding has been used to do so. To see this, imagine re-parametrizing a mixing layer with a softmax. If padding has been used to fold it, then only a subset of parameters must sum to one. To implement this, I assumed the re-parametrization function must take both a tensor and an optional fold mask (a boolean tensor masking the actual parameters).
2. In order to implement the backtrack algorithm next (e.g., for sampling, mpe), I made the fold mask above an optional attribute of the layers. Indeed, we need this to mask the actual parameters of the sum units.
3. I have removed the prod_exp implementation to simplify the current code for now. Before merging I will run some benchmarks to better understand how much faster the prod_exp implementation is. Do we already have some benchmarks on this? It seems to me we did not find a case where that tiny portion of parameters space is useful, especially if we allow for unnormalized parameters. Also, if we have CP layers with products with more than two inputs, it is always better to compute them in log-space for numerical stability.

Additional features we are now able to implement easily

1. Region graphs where partition nodes are not necessarily binary. Implementing this requires reviewing the file format, as we assumed only "left" and right" regions.
2. Implement methods fold and unfold in cirkit.models.functional, thus making folding optional. The unfold method would enable us to cache intermediate computations, e.g., for compression or to do fast inverse transform sampling.

Closes #113.
Closes #116.

[loreloc]

Benchmark results for this PR.
It seems we are slightly faster now than July's version (#110), e.g., ~+6% on 28x28 PD architecture with Delta=5.

PD D7
Number of parameters: 103151628
Time (ms): 69.114+-0.589
Memory (MiB): 4711.899+-0.000

PD D5
Number of parameters: 105730068
Time (ms): 115.475+-1.899
Memory (MiB): 5051.841+-0.000

QT SD
Number of parameters: 103962625
Time (ms): 97.953+-2.027
Memory (MiB): 4726.975+-0.000

QT
Number of parameters: 105419780
Time (ms): 134.501+-1.737
Memory (MiB): 4768.519+-0.000

BT D4 R16
Number of parameters: 103120928
Time (ms): 65.111+-1.497
Memory (MiB): 4712.148+-0.000

[loreloc]

This is not merged yet because I plan to implement more fine-grained tests for each layer, rather than just testing a PC.

[loreloc]

• Added a bunch of tests for layers.
• Added tests for back propagation for both densely and sparsely (e.g., with heterogeneous layer arities) folded tensorized circuits.

[lkct]

some notes for myself. some for discussion.

[lkct]

pad can be fused into cat?