Assignments involving modelling and analysis of components of a modern computer, done as a part of a graduate level Computer Architecture Course at IIT Madras (Jul-Nov 2021).
This work was done in collaboration with Arjun.
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CacheEval: Reverse Engineering the Block Size and Associativity of L1 Cache of a desktop PC by observing the variation in access latency.
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SimCache: Python-based Simulator of a Uniprocessor cache supporting Direct Mapped, Fully Associative and Set-Associative configurations. Includes implementation of Random, LRU and Pseudo-LRU replacement algorithms.
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AdapPageManage: Implementation of Hybrid Row Buffer Management for DRAMs by extending the command scheduler offered by the USIMM DRAM simulator.
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MMU: Memory Management Unit Simulator in Python implementing multi-level virtual address translation enabling efficient page table management along with LRU replacement for evicting pages and page tables from memory.
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Tournament Branch Predictor: Implementation of the Tournament Branch Predictor, first introduced in the Alpha21264 processor. Uses framework provided by JILP for CBP2016 championship.
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Dynamic Execution Core: Python-based simulator for the Dynamic Execution Core of a Superscalar Out-of-Order Processor. Inspired by Tomasulo's Algorithm, this simulator implements register renaming, in-order dispatch and completion of instructions using dispatch, reservation and reorder buffers.