Digital System Design Lab verilog codes
- Half Adder
- Full Adder (using half adder)
- Full Adder (without using half adder)
- 4 Bit Ripple Carry Adder
- 4 Bit Carry Lookahead Adder
- JK FlipFlop
- D FlipFlop
- D flipflop using SR flipflop with clear input
- T FlipFlop
- Master Slave JK flipflop
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Synchronous
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Asynchronous