Learn RTL Design Together

Repository for Verilog, VHDL, System Verilog building blocks We will upload very basic rtl project
Most of these are well tested and shouldn't have issues. If you notice any issues,please raise it.

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MODULES

Verilog

1	JK FLIPFLOP
2	FULL ADDER
3	ADDER / SUBTRACTOR
4	MULTIPLEXERS
5	BINARY TO GRAY CONVERTER
6	GRAY TO BINARY CONVERTER
7	RIPPLE CARRY ADDER
8	BINARY TO BCD CONVERTER (8-4-2-1)
9	BCD TO BINARY CONVERTER (8-4-2-1)
10	DECIMAL TO AIKEN CONVERTER (2-4-2-1)
11	AIKEN TO DECIMAL (2-4-2-1)
12	BINARY TO EXCESS 3 CONVERTER
13	EXCESS TO BINARY 3 CONVERTER
14	7 SEGMENT DISPLAY DECODER
15	MULTIPLIER
16	DEMULTIPLEXER
17	4 BIT COMPARATOR
18	SR FLIPFLOP
19	T FLIPFLOP
20	SIPO

VHDL

1	JK FLIPFLOP
2	T FLIPFLOP
3	FULL ADDER
4	RIPPLE CARRY ADDER
5	MULTIPLEXERS
6	DEMULTIPLEXER
7	DECODER
8	ENCODER
9	PRIORITY ENCODER