upduino: Fix sim in example testbench

FPGAwars · Mar 18, 2024 · ea69f92 · ea69f92
1 parent 20c060c
commit ea69f92
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diff --git a/icezum/wire/apio.ini b/icezum/wire/apio.ini
@@ -0,0 +1,4 @@
+[env]
+board = icezum
+top-module = main
+
diff --git a/upduino31/testbench/main_tb.v b/upduino31/testbench/main_tb.v
@@ -65,7 +65,7 @@ module main_tb ();
       .count_en(count_en),
       .digit_1(digit_1),
       .digit_10(digit_10),
-      .carry
+      .carry(carry)
   );
 
   initial begin