Merge branch 'master' of https://github.com/FPGAwars/apio-examples

upduino31/pll/.gitignore

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+.sconsign.dblite
+*.vcd
+*.out
+hardware.rpt
+hardware.json
+hardware.asc
+hardware.bin
+hardware.out

upduino31/pll/apio.ini

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+[env]
+board = upduino31
+top-module = main
+

upduino31/pll/info

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+Using the PLL to generate 30Mhz clock from the external 12Mhz clock.

upduino31/pll/leds.v

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+// More info about the primitve led control block SB_RGBA_DRV:
+// https://github.com/tinyvision-ai-inc/UPduino-v3.0/blob/master/RTL/blink_led/rgb_blink.v
+// https://blog.idorobots.org/entries/upduino-fpga-tutorial.html
+
+module leds (
+    input clk,
+    input red_en,
+    input green_en,
+    input blue_en,
+    output wire [2:0] leds_out  // [0]=red, [1]=green, [2]=blue
+);
+
+  // Intensity multiplier for all three channels.
+  localparam integer IntensityAll = 2;
+
+  // Intensity controls in the range [0, 512].
+  localparam integer IntensityRed = 4 * IntensityAll;
+  localparam integer IntensityGreen = 2 * IntensityAll;
+  localparam integer IntensityBlue = 24 * IntensityAll;
+
+  // Frequency divider generate the PWM counter.
+  reg  [15:0] divider;
+
+  // 9 bits PWM counter.
+  wire [ 8:0] pwm_counter = divider[15:7];
+
+  wire        pwm_red = pwm_counter < IntensityRed;
+  wire        pwm_green = pwm_counter < IntensityGreen;
+  wire        pwm_blue = pwm_counter < IntensityBlue;
+
+  // Behavior.
+  always @(posedge clk) begin
+    divider <= divider + 1'b1;
+  end
+
+  // Instantiate the RGB current source primitive.
+  SB_RGBA_DRV #(
+      .CURRENT_MODE("0b1"),  // "0b0" -> full current, "0b1" -> half current.
+      .RGB0_CURRENT("0b000001"),
+      .RGB1_CURRENT("0b000001"),
+      .RGB2_CURRENT("0b000001")
+  ) RGB_DRIVER (
+      .RGBLEDEN(1'b1),
+      .RGB0PWM (green_en && pwm_green),  // Green led input.
+      .RGB1PWM (blue_en & pwm_blue),     // Blue led input.
+      .RGB2PWM (red_en & pwm_red),       // Red led input.
+      .CURREN  (1'b1),
+      .RGB0    (leds_out[1]),            // Current regulated output to green led.
+      .RGB1    (leds_out[2]),            // Current regulated output to blue led.
+      .RGB2    (leds_out[0])             // Current regulated output to red led.
+  );
+
+endmodule

upduino31/pll/main.pcf

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+# Mapping of the design signals to FPGA pins.
+
+# The full Upduino3 PCF file is availble at:
+#  https://github.com/tinyvision-ai-inc/UPduino-v3.0/tree/master/RTL/common
+
+set_io leds_out[0]     41  # Red.
+set_io leds_out[1]     39  # Green.
+set_io leds_out[2]     40  # Blue.
+
+# External 12Mhz clock. Make sure to short the OSC solder jumper.
+set_io ext_clk      20  # 12Mhz in
+
+set_io pll_clk      26  # 30Mhz out
+set_io pll_locked   27
+

upduino31/pll/main.v

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+// This exapmple demonstrates the use of the PLL to generate 30Mhz clock 
+// from the external 12Mhz clock. Make sure to short the OSC jumper 
+// to connect the external clock to the FPGA.
+//
+// Expected results:
+// * 30Mhz output at pin 26 (pll_clk)
+// * Green led blinks at 1Hz.
+
+// IMPORTANT: This example requires to short the OSC solder jumper
+// to feed the external 12Mhz clock to the FPGA.
+
+module main (
+    input  ext_clk,  // 12Mhz in
+    output pll_clk,  // 30Mhz out
+    output pll_locked,
+    output [2:0] leds_out
+);
+
+  reg [24:0] counter;
+  reg led_on;
+
+  // Generate the 1Hz blink
+  always @(posedge pll_clk) begin
+    if (counter >= 30000000 - 1) counter <= 0;
+    else counter <= counter + 1;
+    led_on <= counter <= 10000000;
+  end
+
+  pll pll (
+      .clock_in(ext_clk),
+      .clock_out(pll_clk),
+      .locked(pll_locked)
+  );
+
+   leds leds (
+      .clk(pll_clk),
+      .red_en(1'b0),
+      .green_en(led_on),
+      .blue_en(1'b0),
+      .leds_out(leds_out)
+  );
+
+endmodule
+

upduino31/pll/pll.v

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+ // MOTE: This file was generated with the command:
+ // icepll -m -i 12 -o 30
+
+/**
+ * PLL configuration
+ *
+ * This Verilog module was generated automatically
+ * using the icepll tool from the IceStorm project.
+ * Use at your own risk.
+ *
+ * Given input frequency:        12.000 MHz
+ * Requested output frequency:   30.000 MHz
+ * Achieved output frequency:    30.000 MHz
+ */
+
+module pll (
+    input  clock_in,
+    output clock_out,
+    output locked
+);
+
+  SB_PLL40_CORE #(
+      .FEEDBACK_PATH("SIMPLE"),
+      .DIVR(4'b0000),  // DIVR =  0
+      .DIVF(7'b1001111),  // DIVF = 79
+      .DIVQ(3'b101),  // DIVQ =  5
+      .FILTER_RANGE(3'b001)  // FILTER_RANGE = 1
+  ) uut (
+      .LOCK(locked),
+      .RESETB(1'b1),
+      .BYPASS(1'b0),
+      .REFERENCECLK(clock_in),
+      .PLLOUTCORE(clock_out)
+  );
+
+endmodule
+

upduino31/testbench/apio.ini

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+[env]
+board = upduino31
+top-module = main
+

upduino31/testbench/bcd_counter.v

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+// A 4 bit BCD counter with synchronous clock and carry out. 
+// It Counts up on positive edge of clk, when count_en is high.
+
+module bcd_counter (
+    input clk,
+    input reset,
+    input count_en,
+    output reg [3:0] data_out,
+    output carry
+);
+
+  // Behavior.
+  always @(posedge clk) begin
+    if (reset || data_out > 9) begin
+      // Case 1: Reset or invalid state.;
+      data_out <= 0;
+    end else if (count_en) begin
+      // Case 1: Increment, with optional overflow from 9 to 0.
+      data_out <= (data_out == 9) ? 0 : data_out + 1;
+    end
+  end
+
+  assign carry = !reset && count_en && (data_out == 9);
+
+endmodule

upduino31/testbench/info

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+A testbench with an automatic testing a sequential module.

upduino31/testbench/main.pcf

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+# Mapping of the design signals to FPGA pins.
+
+# The full Upduino3 PCF file is availble at:
+#  https://github.com/tinyvision-ai-inc/UPduino-v3.0/tree/master/RTL/common
+
+set_io clk          10
+set_io reset        12
+set_io count_en     21
+set_io carry        13
+
+set_io digit_1[0]   19
+set_io digit_1[1]   18 
+set_io digit_1[2]   11
+set_io digit_1[3]    9
+
+set_io digit_10[0]  44 
+set_io digit_10[1]   4
+set_io digit_10[2]   3
+set_io digit_10[3]  48
+

upduino31/testbench/main.v

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+// Generates a RGB blinking pattern. Uses the internal oscilator.
+module main (
+  input clk,
+  input reset,
+  input count_en,
+  output [3:0] digit_1,
+  output [3:0] digit_10,
+  output carry
+);
+
+wire carry_1;
+
+bcd_counter count_1 (
+    .clk(clk),
+    .reset(reset),
+    .count_en(count_en),
+    .data_out(digit_1),
+    .carry(carry_1)
+);
+
+bcd_counter count_10 (
+    .clk(clk),
+    .reset(reset),
+    .count_en(carry_1),
+    .data_out(digit_10),
+    .carry(carry)
+);
+
+endmodule

upduino31/testbench/main_tb.gtkw

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+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Sat Mar  2 22:47:15 2024
+[*]
+[dumpfile] "main_tb.vcd"
+[dumpfile_mtime] "Sat Mar  2 22:46:12 2024"
+[dumpfile_size] 7168
+[savefile] "main_tb.gtkw"
+[timestart] 0
+[size] 1440 900
+[pos] -1 -26
+*-22.382421 3100000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+[markername] AA
+[markername] BB
+[markername] CC
+[markername] DD
+[markername] EE
+[markername] FF
+[markername] GG
+[markername] HH
+[markername] II
+[markername] JJ
+[markername] KK
+[markername] LL
+[markername] MM
+[markername] NN
+[markername] OO
+[markername] PP
+[markername] QQ
+[markername] RR
+[markername] SS
+[markername] TT
+[markername] UU
+[markername] VV
+[markername] WW
+[markername] XX
+[markername] YY
+[markername] ZZ
+[treeopen] main_tb.
+[sst_width] 253
+[signals_width] 161
+[sst_expanded] 1
+[sst_vpaned_height] 264
+@28
+main_tb.clk
+main_tb.reset
+[color] 3
+main_tb.count_en
+@24
+main_tb.digit_1[3:0]
+@25
+main_tb.digit_10[3:0]
+@28
+main_tb.carry
+@24
+main_tb.carry_count[5:0]
+[pattern_trace] 1
+[pattern_trace] 0