Fixed typos + added tested access layer

access/access.vhd

@@ -0,0 +1,69 @@
+--*******************************
+--* TITLE: Access (sender) 	*
+--* TYPE: Component 		*
+--* AUTHOR: Dylan Van Assche 	*
+--* DATE: 12/10/2017 		*
+--*******************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Access layer API.
+--2)Principle:
+-- Provide an API as access layer
+--3)Inputs:
+-- data, pn_select, rst, clk, clk_en
+--4)Outputs:
+-- pn_start, tx
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+ENTITY access_layer IS
+	PORT (
+		clk : IN std_logic;
+		clk_en : IN std_logic;
+		rst : IN std_logic;
+		data : IN std_logic;
+		pn_select : IN std_logic_vector(1 DOWNTO 0);
+		pn_start : OUT std_logic;
+		tx : OUT std_logic
+	);
+END access_layer;
+ARCHITECTURE behavior OF access_layer IS
+	SIGNAL pn_1_output : std_logic;
+	SIGNAL pn_2_output : std_logic;
+	SIGNAL pn_3_output : std_logic;
+	SIGNAL pn_1_xor : std_logic;
+	SIGNAL pn_2_xor : std_logic;
+	SIGNAL pn_3_xor : std_logic;
+BEGIN
+	pn_1_xor <= pn_1_output XOR data;
+	pn_2_xor <= pn_2_output XOR data;
+	pn_3_xor <= pn_3_output XOR data;
+
+	pngenerator : ENTITY work.pngenerator(behavior)
+	PORT MAP
+	(
+		clk    => clk,
+		clk_en => clk_en,
+		rst => rst,
+		pn_1 => pn_1_output,
+		pn_2 => pn_2_output,
+		pn_3 => pn_3_output,
+		pn_s => pn_start
+	);
+
+	mux : ENTITY work.mux(behavior)
+	PORT MAP
+	(
+		in_0 => data,
+		in_1 => pn_1_xor,
+		in_2 => pn_2_xor,
+		in_3 => pn_3_xor,
+		in_select => pn_select,              
+		output => tx             
+	);
+
+END behavior;

access/access_test.vhd

@@ -0,0 +1,93 @@
+--***************************************
+--* TITLE: Access TESTBENCH (sender) 	*
+--* TYPE: Component 			*
+--* AUTHOR: Dylan Van Assche 		*
+--* DATE: 12/10/2017 			*
+--***************************************
+--********************
+--* DESCRIPTION *
+--********************
+--1)Purpose:
+-- TESTBENCH: Access layer API.
+--2)Principle:
+-- Provide an API as access layer
+--3)Inputs:
+-- rst, clk, clk_en
+--4)Outputs:
+-- output, display_b
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+USE ieee.std_logic_arith.ALL;
+ENTITY access_layer_test IS
+END access_layer_test;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE structural OF access_layer_test IS
+	--initialize signals & constants
+	CONSTANT period   : TIME := 100 ns;
+	CONSTANT delay    : TIME := 10 ns;
+	SIGNAL end_of_sim : BOOLEAN := false;
+	SIGNAL clk        : std_logic;
+	SIGNAL clk_en     : std_logic := '1';
+	SIGNAL rst        : std_logic;
+	SIGNAL data	  : std_logic;
+	SIGNAL pn_select  : std_logic_vector(1 DOWNTO 0);
+	SIGNAL pn_start   : std_logic;
+	SIGNAL tx         : std_logic;
+BEGIN
+--***********
+--* MAPPING *
+--***********
+uut : ENTITY work.access_layer(behavior)
+	PORT MAP
+	(
+		clk       => clk,
+		clk_en    => clk_en,
+		rst       => rst,
+		data	  => data,
+		pn_select => pn_select,
+		pn_start => pn_start,
+		tx => tx
+	);
+-- Only for synchronous components
+clock : PROCESS
+BEGIN
+	clk <= '0';
+	WAIT FOR period/2;
+	LOOP
+		clk <= '0';
+		WAIT FOR period/2;
+		clk <= '1';
+		WAIT FOR period/2;
+		EXIT WHEN end_of_sim;
+	END LOOP;
+	WAIT;
+	END PROCESS clock;
+-- Testbench
+tb : PROCESS
+	-- Reset procedure to initialize the component
+	PROCEDURE reset IS
+	BEGIN
+		rst <= '1';
+		WAIT FOR period * 2;
+		rst <= '0';
+		WAIT FOR period;
+	END reset;
+BEGIN
+	-- Reset at startup
+	reset;
+	-- Test data
+	FOR i IN 0 TO 3 LOOP
+		pn_select <= CONV_STD_LOGIC_VECTOR(i, 2);
+		data <= '1';
+		WAIT FOR period*10;
+	END LOOP;
+	end_of_sim <= true;
+	WAIT;
+END PROCESS;
+END;

access/mux/mux.vhd

@@ -0,0 +1,47 @@
+--*******************************
+--* TITLE: MUX (sender)		*
+--* TYPE: Component 		*
+--* AUTHOR: Dylan Van Assche 	*
+--* DATE: 12/01/2017 		*
+--*******************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Selecting the right PN code
+--2)Principle:
+-- Decode a dipswitch to select the right PN code
+--3)Inputs:
+-- in_0, in_1, in_2, in_3, in_select
+--4)Outputs:
+-- output
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+ENTITY mux IS
+	PORT
+	(
+		in_0, in_1, in_2, in_3  : IN std_logic; -- A std_logic_vector was also a solution but this is easier to connect in the top files.
+		in_select               : IN std_logic_vector(1 DOWNTO 0);
+		output                  : OUT std_logic
+	);
+END mux;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE behavior OF mux IS
+BEGIN
+decode : PROCESS (in_0, in_1, in_2, in_3, in_select)
+BEGIN
+	CASE in_select IS
+		WHEN "00" => output  <= in_0; -- 'input in_0'
+		WHEN "01" => output  <= in_1; -- 'input in_1'
+		WHEN "10" => output  <= in_2; -- 'input in_2'
+		WHEN "11" => output  <= in_3; -- 'input in_3'
+		WHEN OTHERS => output <= in_0; -- fallback
+	END CASE;
+END PROCESS decode;
+END behavior;

access/mux/mux_test.vhd

@@ -0,0 +1,72 @@
+--***************************************
+--* TITLE: MUX TESTBENCH (sender) 	*
+--* TYPE: Component 		 	*
+--* AUTHOR: Dylan Van Assche 	  	*
+--* DATE: 12/01/2017			*
+--***************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Selecting the right PN code
+--2)Principle:
+-- Decode a dipswitch to select the right PN code
+--3)Inputs:
+-- in_0, in_1, in_2, in_3, in_select
+--4)Outputs:
+-- output
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+USE ieee.std_logic_arith.ALL;
+ENTITY mux_test IS
+END mux_test;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE structural OF mux_test IS
+	-- Initialize signals & constants
+	CONSTANT period   : TIME := 100 ns;
+	CONSTANT delay    : TIME := 10 ns;
+	SIGNAL end_of_sim : BOOLEAN := false;
+	SIGNAL in_0       : std_logic;
+	SIGNAL in_1       : std_logic;
+	SIGNAL in_2       : std_logic;
+	SIGNAL in_3       : std_logic;
+	SIGNAL output     : std_logic; 
+	SIGNAL in_select  : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); -- Input 0 is preselected
+BEGIN
+--***********
+--* MAPPING *
+--***********
+uut : ENTITY work.mux(behavior)
+	PORT MAP
+	(
+		in_0    => in_0,
+		in_1    => in_1,
+		in_2    => in_2,
+		in_3    => in_3,
+		in_select => in_select,
+		output => output
+	);
+
+-- Testbench
+tb : PROCESS
+BEGIN
+	-- random data at the inputs
+	in_0 <= '1';
+	in_1 <= '0';
+	in_2 <= '1';
+	in_3 <= '0';
+	-- select each input for 1 CLK cycle
+	FOR i IN 0 TO 3 LOOP
+		in_select <= CONV_STD_LOGIC_VECTOR(i, 2);
+		WAIT FOR period;
+	END LOOP;
+	end_of_sim <= true;
+	WAIT;
+END PROCESS;
+END;

access/pngenerator/pngenerator.vhd

@@ -0,0 +1,78 @@
+--*******************************
+--* TITLE: PNGenerator (sender)	*
+--* TYPE: Component 		*
+--* AUTHOR: Dylan Van Assche 	*
+--* DATE: 12/10/2017 		*
+--*******************************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Generating a PN code
+--2)Principle:
+-- Lineair feedback register to generate a PN code (31 bits)
+--3)Inputs:
+-- rst, clk, clk_en
+--4)Outputs:
+-- pn_s, pn_1, pn_2, pn_3
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+ENTITY pngenerator IS
+	PORT
+	(
+		clk, clk_en, rst : IN std_logic;
+		pn_s, pn_1, pn_2, pn_3  : OUT std_logic -- pn_0 is without PN code
+	);
+	SIGNAL shdata1 : std_logic_vector(4 DOWNTO 0);
+	SIGNAL shdata1_next : std_logic_vector(4 DOWNTO 0);
+	SIGNAL shdata2 : std_logic_vector(4 DOWNTO 0);
+	SIGNAL shdata2_next : std_logic_vector(4 DOWNTO 0);
+	SIGNAL pn_start_next: std_logic;
+	SIGNAL pn_start : std_logic;
+	SIGNAL linear_feedback1 : std_logic;
+	SIGNAL linear_feedback2 : std_logic;
+END;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE behavior OF pngenerator IS
+BEGIN
+	-- Asign signals to outputs and calculate directly the lineair feedback
+	linear_feedback1 <= (shdata1(0) XOR shdata1(3));
+	linear_feedback2 <= ((shdata2(0) XOR shdata2(1)) XOR shdata2(3)) XOR shdata2(4);
+	pn_1 <= shdata1(0);
+	pn_2 <= shdata2(0);
+	pn_3 <= shdata1(0) XOR shdata2(0);
+	pn_s <= pn_start;
+	-- 2-Process: synchronous part
+	pn_sync : PROCESS (clk)
+	BEGIN
+		IF (rising_edge(clk) AND clk_en = '1') THEN
+			IF (rst = '1') THEN -- rst line high, go to initial state
+				shdata1 <= "00010";
+				shdata2 <= "00111";
+				pn_start <= '1';
+			ELSE -- normal operation
+				pn_start <= pn_start_next;
+				shdata1 <= shdata1_next;
+				shdata2 <= shdata2_next;
+			END IF;
+		END IF;
+	END PROCESS pn_sync;
+	-- 2-Process: combinatoric part
+	pn_comb : PROCESS (shdata1, shdata2, linear_feedback1, linear_feedback2)
+	BEGIN
+		-- shift the data and load the lineair feedback
+		shdata1_next <= linear_feedback1 & shdata1(4 DOWNTO 1);
+		shdata2_next <= linear_feedback2 & shdata2(4 DOWNTO 1);
+		-- next value is the start value, prepare pn_start already
+		IF (shdata1 = "00100") THEN 
+			pn_start_next <= '1';
+		ELSE
+			pn_start_next <= '0';
+		END IF;
+	END PROCESS pn_comb;
+END behavior;